% -*- mode: latex; TeX-master: "Vorbis_I_spec"; -*-
%!TEX root = Vorbis_I_spec.tex
% $Id$
\section{Floor type 1 setup and decode} \label{vorbis:spec:floor1}

\subsection{Overview}

Vorbis floor type one uses a piecewise straight-line representation to
encode a spectral envelope curve. The representation plots this curve
mechanically on a linear frequency axis and a logarithmic (dB)
amplitude axis. The integer plotting algorithm used is similar to
Bresenham's algorithm.

\subsection{Floor 1 format}

\subsubsection{model}

Floor type one represents a spectral curve as a series of
line segments.  Synthesis constructs a floor curve using iterative
prediction in a process roughly equivalent to the following simplified
description:

\begin{itemize}
 \item  the first line segment (base case) is a logical line spanning
from x_0,y_0 to x_1,y_1 where in the base case x_0=0 and x_1=[n], the
full range of the spectral floor to be computed.

\item the induction step chooses a point x_new within an existing
logical line segment and produces a y_new value at that point computed
from the existing line's y value at x_new (as plotted by the line) and
a difference value decoded from the bitstream packet.

\item floor computation produces two new line segments, one running from
x_0,y_0 to x_new,y_new and from x_new,y_new to x_1,y_1. This step is
performed logically even if y_new represents no change to the
amplitude value at x_new so that later refinement is additionally
bounded at x_new.

\item the induction step repeats, using a list of x values specified in
the codec setup header at floor 1 initialization time.  Computation
is completed at the end of the x value list.

\end{itemize}

Consider the following example, with values chosen for ease of
understanding rather than representing typical configuration:

For the below example, we assume a floor setup with an [n] of 128.
The list of selected X values in increasing order is
0,16,32,48,64,80,96,112 and 128.  In list order, the values interleave
as 0, 128, 64, 32, 96, 16, 48, 80 and 112.  The corresponding
list-order Y values as decoded from an example packet are 110, 20, -5,
-45, 0, -25, -10, 30 and -10.  We compute the floor in the following
way, beginning with the first line:

\begin{center}
\includegraphics[width=8cm]{floor1-1}
\captionof{figure}{graph of example floor}
\end{center}

We now draw new logical lines to reflect the correction to new_Y, and
iterate for X positions 32 and 96:

\begin{center}
\includegraphics[width=8cm]{floor1-2}
\captionof{figure}{graph of example floor}
\end{center}

Although the new Y value at X position 96 is unchanged, it is still
used later as an endpoint for further refinement.  From here on, the
pattern should be clear; we complete the floor computation as follows:

\begin{center}
\includegraphics[width=8cm]{floor1-3}
\captionof{figure}{graph of example floor}
\end{center}

\begin{center}
\includegraphics[width=8cm]{floor1-4}
\captionof{figure}{graph of example floor}
\end{center}

A more efficient algorithm with carefully defined integer rounding
behavior is used for actual decode, as described later.  The actual
algorithm splits Y value computation and line plotting into two steps
with modifications to the above algorithm to eliminate noise
accumulation through integer roundoff/truncation.

\subsubsection{header decode}

A list of floor X values is stored in the packet header in interleaved
format (used in list order during packet decode and synthesis).  This
list is split into partitions, and each partition is assigned to a
partition class.  X positions 0 and [n] are implicit and do not belong
to an explicit partition or partition class.

A partition class consists of a representation vector width (the
number of Y values which the partition class encodes at once), a
'subclass' value representing the number of alternate entropy books
the partition class may use in representing Y values, the list of
[subclass] books and a master book used to encode which alternate
books were chosen for representation in a given packet.  The
master/subclass mechanism is meant to be used as a flexible
representation cascade while still using codebooks only in a scalar
context.

\begin{Verbatim}[commandchars=\\\{\}]

  1) [floor1_partitions] = read 5 bits as unsigned integer
  2) [maximum_class] = -1
  3) iterate [i] over the range 0 ... [floor1_partitions]-1 \{

        4) vector [floor1_partition_class_list] element [i] = read 4 bits as unsigned integer

     \}

  5) [maximum_class] = largest integer scalar value in vector [floor1_partition_class_list]
  6) iterate [i] over the range 0 ... [maximum_class] \{

        7) vector [floor1_class_dimensions] element [i] = read 3 bits as unsigned integer and add 1
	8) vector [floor1_class_subclasses] element [i] = read 2 bits as unsigned integer
        9) if ( vector [floor1_class_subclasses] element [i] is nonzero ) \{

             10) vector [floor1_class_masterbooks] element [i] = read 8 bits as unsigned integer

           \}

       11) iterate [j] over the range 0 ... (2 exponent [floor1_class_subclasses] element [i]) - 1 \{

             12) array [floor1_subclass_books] element [i],[j] =
                 read 8 bits as unsigned integer and subtract one
           \}
      \}

 13) [floor1_multiplier] = read 2 bits as unsigned integer and add one
 14) [rangebits] = read 4 bits as unsigned integer
 15) vector [floor1_X_list] element [0] = 0
 16) vector [floor1_X_list] element [1] = 2 exponent [rangebits];
 17) [floor1_values] = 2
 18) iterate [i] over the range 0 ... [floor1_partitions]-1 \{

       19) [current_class_number] = vector [floor1_partition_class_list] element [i]
       20) iterate [j] over the range 0 ... ([floor1_class_dimensions] element [current_class_number])-1 \{
             21) vector [floor1_X_list] element ([floor1_values]) =
                 read [rangebits] bits as unsigned integer
             22) increment [floor1_values] by one
           \}
     \}

 23) done
\end{Verbatim}

An end-of-packet condition while reading any aspect of a floor 1
configuration during setup renders a stream undecodable.  In addition,
a \varname{[floor1_class_masterbooks]} or
\varname{[floor1_subclass_books]} scalar element greater than the
highest numbered codebook configured in this stream is an error
condition that renders the stream undecodable.  All vector
[floor1_x_list] element values must be unique within the vector; a
non-unique value renders the stream undecodable.

\paragraph{packet decode} \label{vorbis:spec:floor1-decode}

Packet decode begins by checking the \varname{[nonzero]} flag:

\begin{Verbatim}[commandchars=\\\{\}]
  1) [nonzero] = read 1 bit as boolean
\end{Verbatim}

If \varname{[nonzero]} is unset, that indicates this channel contained
no audio energy in this frame.  Decode immediately returns a status
indicating this floor curve (and thus this channel) is unused this
frame.  (A return status of 'unused' is different from decoding a
floor that has all points set to minimum representation amplitude,
which happens to be approximately -140dB).

Assuming \varname{[nonzero]} is set, decode proceeds as follows:

\begin{Verbatim}[commandchars=\\\{\}]
  1) [range] = vector \{ 256, 128, 86, 64 \} element ([floor1_multiplier]-1)
  2) vector [floor1_Y] element [0] = read \link{vorbis:spec:ilog}{ilog}([range]-1) bits as unsigned integer
  3) vector [floor1_Y] element [1] = read \link{vorbis:spec:ilog}{ilog}([range]-1) bits as unsigned integer
  4) [offset] = 2;
  5) iterate [i] over the range 0 ... [floor1_partitions]-1 \{

       6) [class] = vector [floor1_partition_class]  element [i]
       7) [cdim]  = vector [floor1_class_dimensions] element [class]
       8) [cbits] = vector [floor1_class_subclasses] element [class]
       9) [csub]  = (2 exponent [cbits])-1
      10) [cval]  = 0
      11) if ( [cbits] is greater than zero ) \{

             12) [cval] = read from packet using codebook number
                 (vector [floor1_class_masterbooks] element [class]) in scalar context
          \}

      13) iterate [j] over the range 0 ... [cdim]-1 \{

             14) [book] = array [floor1_subclass_books] element [class],([cval] bitwise AND [csub])
             15) [cval] = [cval] right shifted [cbits] bits
	     16) if ( [book] is not less than zero ) \{

	           17) vector [floor1_Y] element ([j]+[offset]) = read from packet using codebook
                       [book] in scalar context

                 \} else [book] is less than zero \{

	           18) vector [floor1_Y] element ([j]+[offset]) = 0

                 \}
          \}

      19) [offset] = [offset] + [cdim]

     \}

 20) done
\end{Verbatim}

An end-of-packet condition during curve decode should be considered a
nominal occurrence; if end-of-packet is reached during any read
operation above, floor decode is to return 'unused' status as if the
\varname{[nonzero]} flag had been unset at the beginning of decode.

Vector \varname{[floor1_Y]} contains the values from packet decode
needed for floor 1 synthesis.

\paragraph{curve computation} \label{vorbis:spec:floor1-synth}

Curve computation is split into two logical steps; the first step
derives final Y amplitude values from the encoded, wrapped difference
values taken from the bitstream.  The second step plots the curve
lines.  Also, although zero-difference values are used in the
iterative prediction to find final Y values, these points are
conditionally skipped during final line computation in step two.
Skipping zero-difference values allows a smoother line fit.

Although some aspects of the below algorithm look like inconsequential
optimizations, implementors are warned to follow the details closely.
Deviation from implementing a strictly equivalent algorithm can result
in serious decoding errors.

\begin{description}
\item[step 1: amplitude value synthesis]

Unwrap the always-positive-or-zero values read from the packet into
+/- difference values, then apply to line prediction.

\begin{Verbatim}[commandchars=\\\{\}]
  1) [range] = vector \{ 256, 128, 86, 64 \} element ([floor1_multiplier]-1)
  2) vector [floor1_step2_flag] element [0] = set
  3) vector [floor1_step2_flag] element [1] = set
  4) vector [floor1_final_Y] element [0] = vector [floor1_Y] element [0]
  5) vector [floor1_final_Y] element [1] = vector [floor1_Y] element [1]
  6) iterate [i] over the range 2 ... [floor1_values]-1 \{

       7) [low_neighbor_offset] = \link{vorbis:spec:low:neighbor}{low_neighbor}([floor1_X_list],[i])
       8) [high_neighbor_offset] = \link{vorbis:spec:high:neighbor}{high_neighbor}([floor1_X_list],[i])

       9) [predicted] = \link{vorbis:spec:render:point}{render_point}( vector [floor1_X_list] element [low_neighbor_offset],
				      vector [floor1_final_Y] element [low_neighbor_offset],
                                      vector [floor1_X_list] element [high_neighbor_offset],
				      vector [floor1_final_Y] element [high_neighbor_offset],
                                      vector [floor1_X_list] element [i] )

      10) [val] = vector [floor1_Y] element [i]
      11) [highroom] = [range] - [predicted]
      12) [lowroom]  = [predicted]
      13) if ( [highroom] is less than [lowroom] ) \{

            14) [room] = [highroom] * 2

          \} else [highroom] is not less than [lowroom] \{

            15) [room] = [lowroom] * 2

          \}

      16) if ( [val] is nonzero ) \{

            17) vector [floor1_step2_flag] element [low_neighbor_offset] = set
            18) vector [floor1_step2_flag] element [high_neighbor_offset] = set
            19) vector [floor1_step2_flag] element [i] = set
            20) if ( [val] is greater than or equal to [room] ) \{

                  21) if ( [highroom] is greater than [lowroom] ) \{

                        22) vector [floor1_final_Y] element [i] = [val] - [lowroom] + [predicted]

		      \} else [highroom] is not greater than [lowroom] \{

                        23) vector [floor1_final_Y] element [i] = [predicted] - [val] + [highroom] - 1

                      \}

                \} else [val] is less than [room] \{

		  24) if ([val] is odd) \{

                        25) vector [floor1_final_Y] element [i] =
                            [predicted] - (([val] + 1) divided by  2 using integer division)

                      \} else [val] is even \{

                        26) vector [floor1_final_Y] element [i] =
                            [predicted] + ([val] / 2 using integer division)

                      \}

                \}

          \} else [val] is zero \{

            27) vector [floor1_step2_flag] element [i] = unset
            28) vector [floor1_final_Y] element [i] = [predicted]

          \}

     \}

 29) done

\end{Verbatim}

\item[step 2: curve synthesis]

Curve synthesis generates a return vector \varname{[floor]} of length
\varname{[n]} (where \varname{[n]} is provided by the decode process
calling to floor decode).  Floor 1 curve synthesis makes use of the
\varname{[floor1_X_list]}, \varname{[floor1_final_Y]} and
\varname{[floor1_step2_flag]} vectors, as well as [floor1_multiplier]
and [floor1_values] values.

Decode begins by sorting the scalars from vectors
\varname{[floor1_X_list]}, \varname{[floor1_final_Y]} and
\varname{[floor1_step2_flag]} together into new vectors
\varname{[floor1_X_list]'}, \varname{[floor1_final_Y]'} and
\varname{[floor1_step2_flag]'} according to ascending sort order of the
values in \varname{[floor1_X_list]}.  That is, sort the values of
\varname{[floor1_X_list]} and then apply the same permutation to
elements of the other two vectors so that the X, Y and step2_flag
values still match.

Then compute the final curve in one pass:

\begin{Verbatim}[commandchars=\\\{\}]
  1) [hx] = 0
  2) [lx] = 0
  3) [ly] = vector [floor1_final_Y]' element [0] * [floor1_multiplier]
  4) iterate [i] over the range 1 ... [floor1_values]-1 \{

       5) if ( [floor1_step2_flag]' element [i] is set ) \{

             6) [hy] = [floor1_final_Y]' element [i] * [floor1_multiplier]
 	     7) [hx] = [floor1_X_list]' element [i]
             8) \link{vorbis:spec:render:line}{render_line}( [lx], [ly], [hx], [hy], [floor] )
             9) [lx] = [hx]
	    10) [ly] = [hy]
          \}
     \}

 11) if ( [hx] is less than [n] ) \{

        12) \link{vorbis:spec:render:line}{render_line}( [hx], [hy], [n], [hy], [floor] )

     \}

 13) if ( [hx] is greater than [n] ) \{

            14) truncate vector [floor] to [n] elements

     \}

 15) for each scalar in vector [floor], perform a lookup substitution using
     the scalar value from [floor] as an offset into the vector \link{vorbis:spec:floor1:inverse:dB:table}{[floor1_inverse_dB_static_table]}

 16) done

\end{Verbatim}

\end{description}


\section{Result}

\subsection{Measurements for spring constant}

First we get the raw length measurement data in Table~\ref{s1}.
\begin{table}[H]
	\centering
	\begin{tabular}{|p{0.7cm}|p{3cm}||p{0.7cm}|p{3cm}||p{0.7cm}|p{3cm}|}
	\hline
	\multicolumn{2}{|c|}{spring 1 [cm] $\pm$ 0.01 [cm]} &
	\multicolumn{2}{|c|}{spring 2 [cm] $\pm$ 0.01 [cm]} &
	\multicolumn{2}{|c|}{serial   [cm] $\pm$ 0.01 [cm]} \\ \hline
	$L_0$ & 0.00  & $L_0$ & 0.00  & $L_0$ & 20.00 \\ \hline
	$L_1$ & 2.00  & $L_1$ & 2.01  & $L_1$ & 23.96 \\ \hline
	$L_2$ & 3.96  & $L_2$ & 4.00  & $L_2$ & 27.94 \\ \hline
	$L_3$ & 5.96  & $L_3$ & 6.03  & $L_3$ & 31.90 \\ \hline
	$L_4$ & 8.02  & $L_4$ & 8.06  & $L_4$ & 36.40 \\ \hline
	$L_5$ & 10.04 & $L_5$ & 10.08 & $L_5$ & 39.94 \\ \hline
	$L_6$ & 12.02 & $L_6$ & 12.10 & $L_6$ & 44.02 \\ \hline
	\end{tabular}
	\caption{Spring constant measurement data}
\label{s1}
\end{table}

Then we can calculate the change amount of the spring length by $\Delta L_i=L_i-L_0$ and get Table \ref{s2}.

\begin{table}[H]
	\centering
	\begin{tabular}{|p{0.7cm}|p{3cm}||p{0.7cm}|p{3cm}||p{0.7cm}|p{3cm}|}
	\hline
	\multicolumn{2}{|c|}{spring 1 [cm] $\pm$ 0.01 [cm]} &
	\multicolumn{2}{|c|}{spring 2 [cm] $\pm$ 0.01 [cm]} &
	\multicolumn{2}{|c|}{serial   [cm] $\pm$ 0.01 [cm]} \\ \hline
	$\Delta L_1$ & 2.00  & $\Delta L_1$ & 2.01  & $\Delta L_1$ & 3.96  \\ \hline
	$\Delta L_2$ & 3.96  & $\Delta L_2$ & 4.00  & $\Delta L_2$ & 7.94  \\ \hline
	$\Delta L_3$ & 5.96  & $\Delta L_3$ & 6.03  & $\Delta L_3$ & 11.90 \\ \hline
	$\Delta L_4$ & 8.02  & $\Delta L_4$ & 8.06  & $\Delta L_4$ & 16.40 \\ \hline
	$\Delta L_5$ & 10.04 & $\Delta L_5$ & 10.08 & $\Delta L_5$ & 19.94 \\ \hline
	$\Delta L_6$ & 12.02 & $\Delta L_6$ & 12.10 & $\Delta L_6$ & 24.02 \\ \hline
	\end{tabular}
	\caption{Calculated Spring constant measurement data}
\label{s2}
\end{table}

We get the mass of the weight object for every $\Delta L_i$ in Table
\ref{massofweight}.

Since the acceleration due to gravity in Shanghai is $9.794 m/s^2$, we calculated
the weights of each weight object from its mass, as shown in Table
\ref{gravityofweight}.

\begin{minipage}{0.5\linewidth}
	\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|}
	\hline
	\multicolumn{2}{|c|}{m [g] $\pm$ 0.01 [g]} \\ \hline
	1 & 4.65  \\ \hline
	2 & 9.32  \\ \hline
	3 & 14.17 \\ \hline
	4 & 18.99 \\ \hline
	5 & 23.80 \\ \hline
	6 & 28.51 \\ \hline
	\end{tabular}
	\caption{Mass measurement data.}
\label{massofweight}
	\end{table}
\end{minipage}
%
\begin{minipage}{0.5\linewidth}
	\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|}
	\hline
	\multicolumn{2}{|c|}{F [N] $\pm$ 0.0001 [N]} \\ \hline
	1  & 0.0455  \\ \hline
	2  & 0.0913  \\ \hline
	3  & 0.1388  \\ \hline
	4  & 0.1860  \\ \hline
	5  & 0.2331  \\ \hline
	6  & 0.2792  \\ \hline
	\end{tabular}
	\caption{Weight measurement data.}
\label{gravityofweight}
\end{table}
\end{minipage}

% =====================================
% NOTE: Spring 1
For Spring 1, we can have its length change data versus the force affected on it
data.

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|c|}
	\hline
	No. & length [cm] $\pm$ 0.01 [cm] & F [N] $\pm$ 0.0001 [N] \\ \hline
	$\Delta L_1$ & 2.00  &  0.0455  \\ \hline
	$\Delta L_2$ & 3.96  &  0.0913  \\ \hline
	$\Delta L_3$ & 5.96  &  0.1388  \\ \hline
	$\Delta L_4$ & 8.02  &  0.1860  \\ \hline
	$\Delta L_5$ & 10.04 &  0.2331  \\ \hline
	$\Delta L_6$ & 12.02 &  0.2792  \\ \hline
	\end{tabular}
	\caption{$\Delta L$  vs. Force for Spring 1}
\label{s1df}
\end{table}

Then we use MATLAB fit tools to find $k_1$

\begin{figure}[H]
	\centering
	\includegraphics[width=13cm]{matlab/fitfig/k1}
	\caption{Fit curve of spring 1}
\end{figure}

$$ k_1 = 2.3311 \pm 0.013 [N/m] $$
$$ u_{k_1,r} = 0.55 \% $$

Goodness of fit:
\begin{quote}
	\centering
	SSE: 6.091e-07				\\
	R-square: 1					\\
	Adjusted R-square: 1 		\\
	RMSE: 0.0003902 			\\
\end{quote}

% =====================================
% NOTE: Spring 2
For Spring 2, we can have its length change data versus the force affected on it
data.

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|c|}
	\hline
	No. & length [cm] $\pm$ 0.01 [cm] & F [N] $\pm$ 0.0001 [N] \\ \hline
	$\Delta L_1$ & 2.01  &  0.0455  \\ \hline
	$\Delta L_2$ & 4.00  &  0.0913  \\ \hline
	$\Delta L_3$ & 6.03  &  0.1388  \\ \hline
	$\Delta L_4$ & 8.06  &  0.1860  \\ \hline
	$\Delta L_5$ & 10.08 &  0.2331  \\ \hline
	$\Delta L_6$ & 12.10 &  0.2792  \\ \hline
	\end{tabular}
	\caption{$\Delta L$  vs. Force for Spring 2}
\label{s2df}
\end{table}

Then we use MATLAB fit tools to find $k_2$

\begin{figure}[H]
	\centering
	\includegraphics[width=13cm]{matlab/fitfig/k2}
	\caption{Fit curve of spring 2}
\end{figure}

$$k_2 =  2.3206 \pm 0.0105 [N/m] $$
$$ u_{k_2,r} = 0.45 \% $$

Goodness of fit:
\begin{quote}
	\centering
	SSE: 4.305e-07 				\\
	R-square: 1 				\\
	Adjusted R-square: 1 		\\
 	RMSE: 0.0003281 			\\
\end{quote}

% =====================================
% NOTE: Spring serial
For serial, we can have its length change data versus the force affected on it
data.

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|c|}
	\hline
	No. & length [cm] $\pm$ 0.01 [cm] & F [N] $\pm$ 0.0001 [N] \\ \hline
	$\Delta L_1$ & 3.96  &  0.0455  \\ \hline
	$\Delta L_2$ & 7.94  &  0.0913  \\ \hline
	$\Delta L_3$ & 11.90 &  0.1388  \\ \hline
	$\Delta L_4$ & 16.40 &  0.1860  \\ \hline
	$\Delta L_5$ & 19.94 &  0.2331  \\ \hline
	$\Delta L_6$ & 24.02 &  0.2792  \\ \hline
	\end{tabular}
	\caption{$\Delta L$  vs. Force for serial}
\label{ssdf}
\end{table}

Then we use MATLAB fit tools to find $k_3$ , in other words, the $k$ of the serial string.

\begin{figure}[H]
	\centering
	\includegraphics[width=13cm]{matlab/fitfig/k3}
	\caption{Fit curve of spring serial}
\end{figure}

$$k_3 = 1.165 \pm 0.0380 [N/m] $$
$$ u_{k_3,r} = 3.26 \% $$

Goodness of fit:
\begin{quote}
	\centering
	SSE: 2.144e-05 				\\
	R-square: 0.9994 			\\
	Adjusted R-square: 0.9993 	\\
	RMSE: 0.002315 				\\
\end{quote}

% NOTE: k cal

By theory, we can calculate $k_3$, i.e. the $k$ of the spring serial by
$$ k_{3,theory} = \frac{k_1 \cdot k_2 }{k_1 + k_2} =  1.1629 $$

Compared with $k_3 = 1.1649$  from the experiment,
$$ u_{k_{3,theory},k_3} = \frac{1.1649 - 1.1629}{1.1629} \cdot 100 \%  = 0.17 \% $$
The theory data is close to the experiment data

\subsection{Relation between the period $T$ and the mass $M$}

In this part, we investigate in finding the relation between the period $T$ and
the mass $M$.
First, we need to collect the mass data needed later for the fit. Shown in Table~\ref{dataMass}.

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|}
	\hline
	\multicolumn{2}{|c|}{Mass of the object [g] $\pm$ 0.01 [g]} \\ \hline
	object with I-shape $m_{I-obj}$  & 176.87 \\ \hline
	object with U-shape $m_{U-obj}$  & 188.16 \\ \hline
	spring 1 			$m_{spr1}$ & 11.23 \\ \hline
	spring 2 			$m_{spr2}$ & 10.54 \\ \hline \hline
	\multicolumn{2}{|c|}{Mass of the object [g] $\pm$ 0.015 [g]} \\ \hline
	equivalent mass		$M_{0,I} = m_{I-obj} + \frac{1}{3} m_{spr1} + \frac{1}{3} m_{spr2} $ & 184.13 \\ \hline
	equivalent mass		$M_{0,U} = m_{U-obj} + \frac{1}{3} m_{spr1} + \frac{1}{3} m_{spr2} $ & 195.42 \\ \hline
	\end{tabular}
	\caption{Mass measurement data}
\label{dataMass}
\end{table}

The the period $T$ measured in different situations are shown in Table~\ref{dataTime}.

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c||c|c||c|c|}
	\hline
	\multicolumn{6}{|c|}{10 periods [ms] $\pm$ 0.1 [ms]} \\ \hline
    \multicolumn{2}{|c||}{horizontal}  &
     \multicolumn{2}{|c||}{incline 1}  &
     \multicolumn{2}{|c|}{incline 2}  \\ \hline
	$m_1$ & 12560.4 & $m_1$ & 12557.8 & $m_1$ & 12560.9 \\ \hline
	$m_2$ & 12718.2 & $m_2$ & 12711.1 & $m_2$ & 12722.0 \\ \hline
	$m_3$ & 12878.4 & $m_3$ & 12872.2 & $m_3$ & 12885.9 \\ \hline
	$m_4$ & 13021.2 & $m_4$ & 13030.3 & $m_4$ & 13034.7 \\ \hline
	$m_5$ & 13189.2 & $m_5$ & 13186.0 & $m_5$ & 13179.2 \\ \hline
	$m_6$ & 13326.5 & $m_6$ & 13333.3 & $m_6$ & 13336.9 \\ \hline
	\end{tabular}
	\caption{Measurement data for the $T$ vs. $M$ relation}
\label{dataTime}
\end{table}

Recall we have the mass data.
We need to add the mass of object with I-shape to each $m_i$
Thus, we can have,

\begin{table}[H]
\centering
\begin{tabular}{|c|c|}
\hline
\multicolumn{2}{|c|}{m [g] $\pm$ 0.01 [g]} \\ \hline
1 & 181.52 \\ \hline
2 & 186.19 \\ \hline
3 & 191.04 \\ \hline
4 & 195.86 \\ \hline
5 & 200.67 \\ \hline
6 & 205.38 \\ \hline
\end{tabular}
\caption{Mass measurement data with I-shape and the object.}
\label{massofweight1}
\end{table}

Thus, for horizontal situation, we can get the following table.

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|}
	\hline
	mass [g] $\pm$ 0.01 [g] & $T^2$ [$s^2$] $\pm$ 0.00001 [$s^2$] \\ \hline
	$m_1$ = 181.52  & 1.57763 \\ \hline
	$m_2$ = 186.19  & 1.61752 \\ \hline
	$m_3$ = 191.04  & 1.65853 \\ \hline
	$m_4$ = 195.86  & 1.69551 \\ \hline
	$m_5$ = 200.67  & 1.73954 \\ \hline
	$m_6$ = 205.38  & 1.77595 \\ \hline
	\end{tabular}
	\caption{$T^2$ vs. $M$ for horizontal situation}
\label{T2vsM_0}
\end{table}

Then we use MATLAB fit tools to find $slope_{h}$

\begin{figure}[H]
	\centering
	\includegraphics[width=13cm]{matlab/fitfig/m1}
	\caption{Fit curve of $T^2$ vs. $M$ for horizontal situation}
\end{figure}

$$slope_{h} = 8.3233 \pm 0.2235 [s^2/kg] $$
$$ u_{slope_{h},r} = 2.69 \% $$

Goodness of fit:
\begin{quote}
	\centering
  SSE: 1.042e-05			 \\
  R-square: 0.9996 		     \\
  Adjusted R-square: 0.9995  \\
  RMSE: 0.001614 		     \\
\end{quote}

For incline 1 situation, we can get the following table.

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|}
	\hline
	mass [g] $\pm$ 0.01 [g] & $T^2$ [$s^2$] $\pm$ 0.00001 [$s^2$] \\ \hline
	$m_1$ = 181.52  & 1.57698 \\ \hline
	$m_2$ = 186.19  & 1.61572 \\ \hline
	$m_3$ = 191.04  & 1.65693 \\ \hline
	$m_4$ = 195.86  & 1.69788 \\ \hline
	$m_5$ = 200.67  & 1.73870 \\ \hline
	$m_6$ = 205.38  & 1.77776 \\ \hline
	\end{tabular}
	\caption{$T^2$ vs. $M$ for incline 1 situation}
\label{T2vsM_1}
\end{table}

Then we use MATLAB fit tools to find $slope_{i1}$, the slope for incline 1.

\begin{figure}[H]
	\centering
	\includegraphics[width=13cm]{matlab/fitfig/m2}
	\caption{Fit curve of $T^2$ vs. $M$ for incline 1 situation}
\end{figure}

$$slope_{i1} = 8.4380 \pm 0.0500 [s^2/kg] $$
$$ u_{slope_{i1},r} = 0.59 \% $$

Goodness of fit:
\begin{quote}
	\centering
  SSE: 5.119e-07 		\\
  R-square: 1 			\\
  Adjusted R-square: 1 	\\
  RMSE: 0.0003577 		\\
\end{quote}

For incline 2 situation, we can get the following table.

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|}
	\hline
	mass [g] $\pm$ 0.01 [g] & $T^2$ [$s^2$] $\pm$ 0.00001 [$s^2$] \\ \hline
	$m_1$ = 181.52  & 1.57776 \\ \hline
	$m_2$ = 186.19  & 1.61849 \\ \hline
	$m_3$ = 191.04  & 1.66046 \\ \hline
	$m_4$ = 195.86  & 1.69903 \\ \hline
	$m_5$ = 200.67  & 1.73691 \\ \hline
	$m_6$ = 205.38  & 1.77872 \\ \hline
	\end{tabular}
	\caption{$T^2$ vs. $M$ for incline 2 situation}
\label{T2vsM_2}
\end{table}

Then we use MATLAB fit tools to find $slope_{i2}$, the slope for incline 2.

\begin{figure}[H]
	\centering
	\includegraphics[width=13cm]{matlab/fitfig/m3}
	\caption{Fit curve of $T^2$ vs. $M$ for incline 2 situation}
\end{figure}

$$slope_{i2} = 8.3467 \pm 0.2185 [s^2/kg] $$
$$ u_{slope_{i2},r} = 2.62 \% $$

Goodness of fit:
\begin{quote}
	\centering
  SSE: 9.958e-06 				\\
  R-square: 0.9996 				\\
  Adjusted R-square: 0.9996 	\\
  RMSE: 0.001578 				\\
\end{quote}

\subsection{Relation between period $T$ and amplitude $A$}

We get the following raw data from the experiment.
\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|c|}
	\hline
	\multicolumn{2}{|c|}{ $A$ [cm] $\pm$ 0.1 [cm]} & ten periods [ms] $\pm$ 0.1 [ms] \\ \hline
	1 &  5.0 & 12566.3 \\ \hline
	2 & 10.0 & 12565.2 \\ \hline
	3 & 15.0 & 12560.9 \\ \hline
	4 & 20.0 & 12562.6 \\ \hline
	5 & 25.0 & 12562.8 \\ \hline
	6 & 30.0 & 12563.7 \\ \hline
	\end{tabular}
	\caption{ten periods $T$ vs. $A$}
\label{TvsAraw}
\end{table}

Then we can drive it into $T$ vs. $A$

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|c|}
	\hline
	\multicolumn{2}{|c|}{ $A$ [m] $\pm$ 0.001 [m]} & $T$ [s] $\pm$ 0.00001 [s] \\ \hline
	1 & 0.050 & 1.25663 \\ \hline
	2 & 0.100 & 1.25652 \\ \hline
	3 & 0.150 & 1.25609 \\ \hline
	4 & 0.200 & 1.25626 \\ \hline
	5 & 0.250 & 1.25628 \\ \hline
	6 & 0.300 & 1.25637 \\ \hline
	\end{tabular}
	\caption{$T$ vs. $A$}
\label{TvsA}
\end{table}

\begin{figure}[H]
	\centering
	\includegraphics[width=13cm]{matlab/fitfig/a1}
	\caption{Fit curve of $T$ vs. $A$}
\end{figure}

$$ k =  -0.001057 \pm 0.0025  [s/m] $$
$$ u_{k,r} = 236.52 \% $$

Goodness of fit:
\begin{quote}
	\centering
 SSE: 1.39e-07 				  \\
 R-square: 0.2602 			  \\
 Adjusted R-square: 0.07529   \\
 RMSE: 0.0001864 			  \\
\end{quote}

For the relative uncertainty is quite large, and R-square is 0.2602, which is not very well,
we can say that $T$ and $A$ do not have a clear linear relation.

\subsection{Relation between $ v_{\max}$ and $A$}

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|}
	\hline
	$x_{in}$ [cm] $\pm$ 0.002 [cm] & $x_{out}$ [cm] $\pm$ 0.002 [cm]  \\ \hline
	0.472 & 1.542 \\ \hline
	0.482 & 1.540 \\ \hline
	0.480 & 1.530 \\ \hline
	\end{tabular}
	\caption{Data of $x_{in}$ and $x_{out}$ for U-shape}
\label{L_inout}
\end{table}

\[
\begin{split}
	x_{in}  & = \frac{1}{3}\sum_{i=1}^{3}x_{in,i}
		      = \frac{0.472 + 0.482 + 0.480}{3}      \\
	        & = (0.4780 \pm 0.003) \quad cm          \\
	u_{r,x_{in}} & = 0.63 \%                         \\
	x_{out} & = \frac{1}{3}\sum_{i=1}^{3}x_{out,i}
	          = \frac{1.542 + 1.540 + 1.530}{3}      \\
	        & = (1.5373 \pm 0.004) \quad cm          \\
	u_{r,x_{out}}& = 0.26  \%
\end{split}
\]

$$ \Delta L = (x_{in} + x_{out})/2 = 1.0076 \pm 0.003 \quad cm $$

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|c|}
	\hline
	\multicolumn{2}{|c|}{ $A$ [cm] $\pm$ 0.1 [cm]} & $\Delta t$ [ms] $\pm$ 0.01 [ms]    \\ \hline
	1  &  5.0 & 42.60 \\ \hline
	2  & 10.0 & 20.56 \\ \hline
	3  & 15.0 & 13.57 \\ \hline
	4  & 20.0 & 10.34 \\ \hline
	5  & 25.0 &  8.25 \\ \hline
	6  & 30.0 &  6.90 \\ \hline
	\end{tabular}
	\caption{Data for the $ {v_{\max}}^2$ vs. $A^2$ relation.}
\label{A_t}
\end{table}

From $ \Delta L = v_{max} \cdot \Delta t $ ,
We can calculate out $ v_{max} $

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|c|c|}
	\hline
	\multicolumn{2}{|c|}{$A$ [cm] $\pm$ 0.1 [cm]}
	& $\Delta t$ [ms] $\pm$ 0.01 [ms]
	& $v_{max}$ [m/s] $\pm$ 0.0001 [m/s] \\ \hline
	1  &  5.0 & 42.60  & 0.2365 \\ \hline
	2  & 10.0 & 20.56  & 0.4901 \\ \hline
	3  & 15.0 & 13.57  & 0.7425 \\ \hline
	4  & 20.0 & 10.34  & 0.9745 \\ \hline
	5  & 25.0 &  8.25  & 1.2213 \\ \hline
	6  & 30.0 &  6.90  & 1.4603 \\ \hline
	\end{tabular}
	\caption{Calculated Data for the $ {v_{\max}}^2$ vs. $A^2$ relation.}
\label{A_t_v}
\end{table}

Finally, we get the relation between$ {v_{\max}}^2$ and $A^2$ .

\begin{table}[H]
	\centering
	\begin{tabular}{|c|c|c|}
	\hline
	\multicolumn{2}{|c|}{$A^2$ [$cm^2$] $\pm$ 0.1 [$cm^2$]}
	&  $v_{max}^2$ [$m^2/s^2$] $\pm$ 0.0001 [$m^2/s^2$] \\ \hline
	1  &  25.0 & 0.0559 \\ \hline
	2  & 100.0 & 0.2402 \\ \hline
	3  & 225.0 & 0.5513 \\ \hline
	4  & 400.0 & 0.9496 \\ \hline
	5  & 625.0 & 1.4917 \\ \hline
	6  & 900.0 & 2.1324 \\ \hline
	\end{tabular}
	\caption{Calculated Data for the $ {v_{\max}}^2$ vs. $A^2$ relation.}
\label{A2_v2}
\end{table}

\begin{figure}[H]
	\centering
	\includegraphics[width=13cm]{matlab/fitfig/av1}
	\caption{Fit curve of $ {v_{\max}}^2$ vs. $A^2$}
\end{figure}

$$ k =   23.6964 \pm 0.3300  $$
$$ u_{k,r} = 1.39 \% $$

Goodness of fit:
\begin{quote}
	\centering
  SSE: 0.0003151 				\\
  R-square: 0.9999          	\\
  Adjusted R-square: 0.9999 	\\
  RMSE: 0.008876    			\\
\end{quote}

Thus, we can find that there is a linear relation between $ {v_{\max}}^2$ and $A^2$.


\documentclass[a4paper,12pt]{report}

\usepackage{amsmath,amsfonts,mathtools}
\usepackage{hyperref}

\usepackage{listings}
\usepackage{color}

\definecolor{dkgreen}{rgb}{0,0.6,0}
\definecolor{gray}{rgb}{0.5,0.5,0.5}
\definecolor{mauve}{rgb}{0.58,0,0.82}

\begin{document}
\title{ECE253 Abridged}
\author{Aman Bhargava}
\date{September 2019}
\maketitle

\tableofcontents

\pagebreak

\chapter{Review: Bit Manipulation}
Have you ever wanted to be a cool computer person who does things with ones and zero's instead of actual letters and numbers like a normal person? If so, this is the right chapter for you!

\section{Converting to and from Different Bases}
Base 10, 2, and 16 are most commonly used. Base 16 is just a way to read base 2 in a more efficient manner. In order to work with bits it's pretty important to know how to convert back and forth because the test is all on paper.

\subsection{Converting from base 10 $\to$ base 2}
You keep dividing by two, keeping track of the remainder. Eventually the number you will be trying to divide by two will be 1. You keep going until it's zero + remainder(1). Then you read the reaminders upward from that final 1.

\subsection{Converting from base 2 $\to$ base 16}
Any hex number can be expressed as 4 binary digits. Make a correspondence table between quadruplets of binary numbers and hex (1-f, inclusive). To convert to base 16 subdivide from right to left in groups of four binary digits. Pad the leftmost part with leading zeros and convert using the table.

\subsection{Converting from base 10 $\to$ base 16 (and vice versa)}
Just go through base 2 fam.

% \chapter{Logic Functions and Logic Gates}
% \section{Or Gate}
% \begin{enumerate}
% \item Symbols
% \item Switch structure
% \item Truth table
% \end{enumerate}

% \section{And Gate}

% \section{Inverter}

% \section{XOR}

\chapter{Boolean Algebra}
Here are the axioms of Boolean Algebra:
\begin{enumerate}
\item $0 \cdot 0 = 0$
\item $1 \cdot 1 = 1$
\item $0 \cdot 1 = 1 \cdot 0 = 0$
\item if $x = 0$, $!x = 1$
\end{enumerate}

\paragraph{Dual Form}
\begin{enumerate}
\item $1 + 1 = 1$
\item $0 + 0 = 0$
\item $1 + 0 = 0 + 1 = 1$
\item if $x = 1$, $!x = 0$
\end{enumerate}

\paragraph{Duality: } In a given logic expression, you can swap $1 \to 0$ and $\cdot \to +$
and the expression is still valid.

\section{Useful Boolean Expression Rules}
\begin{itemize}
\item $x \cdot 0 = 0$
\item $x \cdot 1 = x$
\item $x \cdot x = x$
\item $x \cdot !x = 0$
\item $x \cdot 0 = 0$
\item $!!x = x$
\item $x + 1 = 1$
\item $x + 0 = x$
\item $x + x = x$
\item $x + !x = 1$
\end{itemize}

\paragraph{Distributive Properties: }
$$x \cdot (y + z) = xy + xz$$
$$x + (y \cdot z) = (x+y) \cdot (x+z)$$

% \section{Less Obvious Identities}
% \begin{itemize}
% \item
% \end{itemize}

\section{Sum-of-Products (SOP)}
'Sum' means boolean OR while 'product' means boolean AND.

\paragraph{Min term: } for $n$ variables, term where all variables appear once is a 'minterm'.
Note that variables can either be complimented or uncomplimented.

Any boolean function can be represented by the sum of products of minterms - this is just done
by simply converting the truth table and OR-ing each truth.

Then, you can simplify. Pretty common sense. 'Canonical' just means it's a bunch of midterms
separated by OR's.

\section{Product of Sums (POS)}
\paragraph{Max term: } where all $n$ variables appear OR-d. They can be complimented or
un-complimented.

You can pretty easily make all the valid max terms from a truth table. To generate a POS
expression, you multiply (AND) the maxterms that sum to zero.

% \section{NAND and NOR Logic Networks (TB 2.7)}

% \section{Three-Way Light Control (TB 2.8.1)}

\chapter{How 2 Verilog}
A 3-input multiplexer can be made with two 2-input multiplexers.
Now let's implement this without using two pre-made multiplexers. Let:
\begin{itemize}
\item
\end{itemize}

\paragraph{Notes on Implementation}
\begin{itemize}
\item If you want inputs to be registered from switches, you need to assign them SW[<int>]
\item Likewise, if you want outputs to be registered to LED's, assign them LEDR[<int>]
\end{itemize}

\subsection{Code: 3-Way Multiplexer}

\lstset{frame=tb,
  language=Verilog,
  aboveskip=3mm,
  belowskip=3mm,
  showstringspaces=false,
  columns=flexible,
  basicstyle={\small\ttfamily},
  numbers=none,
  numberstyle=\tiny\color{gray},
  keywordstyle=\color{blue},
  commentstyle=\color{dkgreen},
  stringstyle=\color{mauve},
  breaklines=true,
  breakatwhitespace=true,
  tabsize=3
}

\begin{lstlisting}
module mux2b2to1 (SW, LEDR); //Two bit 2 to 1 multiplexer
   input[4:0] SW, //[4:0] sets switches 0-4 to inputs(?)
   output[1:0] LEDR, //

   wire S;
   wire[1:0] a, b, z; //'two bit wide vector'?

   assign a = SW[1:0],
   assign b = SW[3:2],
   assign s = SW[4],
   assign LEDR = z,

   assign z[0] = (~s&a[0]) | (s&b[0]);
   assign z[1] = (~s & a[1]) | (s&b[1]);

endmodule;
\end{lstlisting}

\paragraph{Can you make the assignment more efficient?}
What if you do this:
\begin{lstlisting}
   // assign z[0] = (~s&a[0]) | (s&b[0]);
   // assign z[1] = (~s & a[1]) | (s&b[1]);
   assign z = (~s&a) | (s&b); // NOT CORRECT
\end{lstlisting}

\paragraph{Because $s$ is only 1-bit and $a, b$ are two bits, $s$ is extended with a \textbf{0},
which makes the logic incorrect!}

\paragraph{General Notes on how Syntax Works:}
\begin{itemize}
\item \textbf{What is 'assign'? } 'assign' just means you're making a connection (alias?) b/w the
two. \textbf{Question: } is this necessary for instantiating the variable?
\item \textbf{Assignment arith.} When you create a verilog wire/input with $x = [a:b]$, the number of bits in
$x$ is $b-a + 1$
\item \textbf{Bit Access: } To access bits, you say $x[n]$ or $x[n:m]$ where $n < m$. The length of the slice
is $n-m +1$
\item \textbf{Concatenation: } If you want to stitch together multiple bits, you use $x = {SW[9:8], SW[1:0]}$. That
statement stitches together two 2-bit chunks ($SW[9:8], SW[1:0]$ to make one 4-bit chunk).
\item \textbf{Order of Operations: } Basically nobody knows... just use parenthesis when you're
not sure. And goes before or, though.
\end{itemize}

\section{Full Adder}
\paragraph{Description: }
Adding in binary is the same as in decimal, just with fewer options. When adding two single bits,
we have three output possibilities: $00, 01, 10$. We call the least significant bit the sum $s$ and
the most significant digit the carry $c$.

Let's see the truth table:
\begin{tabular}{ll|ll}
$x$ & $y$ & $C$ & $s$ \\
\hline
0 & 0 & 0 & 0 \\
0 & 1 & 0 & 1 \\
1 & 0 & 0 & 1 \\
1 & 1 & 1 & 0 \\
\end{tabular}

As you can see, the sum bit is just $x \oplus y$ and the carry bit is $xy$.
This is a \textbf{half adder} because it doesn't accept a carry from the last calculation.

A full adder accepts a carry in $C_{in}$, $x$, and $y$, and outputs sum $s$ and carry out $C_{out}$.

Let's see the truth table:
\begin{tabular}{lll|ll}
$x$ & $y$ & $C_{in}$ & $C_{out}$ & $s$ \\
\hline
0 & 0 & 0 & 0 & 0 \\
0 & 0 & 1 & 0 & 1 \\
0 & 1 & 0 & 0 & 1 \\
0 & 1 & 1 & 1 & 0 \\
1 & 0 & 0 & 0 & 1 \\
1 & 0 & 1 & 1 & 0 \\
1 & 1 & 0 & 1 & 0 \\
1 & 1 & 1 & 1 & 1 \\
\end{tabular}

Therefore $$C_{out} = xy + xC_{in} + yC_{in}$$
and $$s = x \oplus y \oplus C_{in}$$

\paragraph{Ripple Carry Adder: } Then you can string them together by assigning one of these
adders to each bit of the output and passing the carry out to the carry in of the next bit!

\paragraph{Specifics for Ripple Carry Adder: }
\begin{itemize}
\item Max size for output is one more then the two input's sizes because one more order of
magnitude in binary is just doubling the number, and the most you can do when adding two
numbers of equal length is double them.
\item Basically just string them together and you're golden.
\end{itemize}

\paragraph{Review of Outcomes}
\begin{itemize}
\item $Cout = xy + CinX + CinY$
\item $Sum = x \oplus y \oplus z$
\end{itemize}

\paragraph{Now let's make it in verilog!}
\begin{lstlisting}
module fulladder(x, y, Cin, S, Cout);
   input x, y, Cin;
   output S, Cout;

   assign s = x ^ y ^ Cin;
   assign Cout = (x&y) | (Cin&x) | (Cin&y); // Why no wires here? Bc no physical IO's.
\end{lstlisting}

\paragraph{Now we make a 3-bit adder out of full adders in Verilog!}
\begin{lstlisting}
module adder3bit(X, Y, S)
   input[2:0] X, Y;
   output[3:0] S;
   wire[3:0] C; // to connect full adders together

   fulladder U0(X[0], Y[0], C[0], C[1]);
   fulladder U1(X[1], Y[1], C[1], C[2]);
   fulladder U2(X[2], Y[2], C[2], C[3]);

   assign S[3] = C[3]; // Final carry bit is the most significant bit of the sum.
   assign C[0] = 1'b0; // Weird syntax: 1 bit, equal to 0.
endmodule;
\end{lstlisting}

This is structural verilog - we can't immediately see the bigger picture. We see wires and
modules stitched together and we have to figure out what it all means.

\paragraph{Weird constant syntax: }
\begin{itemize}
\item $1'b0$: 1 bit constant, in binary, equal to 0.
\item $4'hF$: 4 bit constant, in hex, equal to F.
\item $4'd9$: 4 bit constant, in decimal, equal to 9.
\item $8'h1E$: 8 bit constant, in hex, equal to 1E.
\end{itemize}

\section{7-Segment Display}
\paragraph{Prompt: } Design a c ircuit with two inputs $x_1$ and $x_0$ representing a
2-bit number $x$. Show $x$ on the 7-segment display (ranges from 0-3 inclusive).

\paragraph{Numbering: } $h_0$ is the top segment. Clockwise increases. $h_6$ is the middle one.

\paragraph{Note on D1-SoC Board: } Logic 0 makes the light turn on for $h_{0-6}$ and 1 makes
it turn off ('active low')

\subsection{Displaying Numbers}
Sections to light up for 0: $h_{0-5}$
Sections to light up for 1: $h_{1-2}$
Sections to light up for 2: $h_{0-1}, h_6, h_{3-4}$
Sections to light up for 3: $h_{0-3}, h_6$

\paragraph{With active low: }
Sections to power for 0: $h_{6}$
Sections to power for 1: $h_{0}, h_{3-6}$
Sections to power for 2: $.$
Sections to power for 3:

\paragraph{Truth Table: }
\begin{tabular}{ll|lllllll}
$x_1$ & $x_2$ & $h_6$ & $h_5$ & $h_4$ & $h_3$ & $h_2$ & $h_1$ & $h_0$  \\
\hline
0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0  \\
0 & 1 & 1 & 1 & 1 & 1 & 0 & 0 & 1  \\
1 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 0  \\
1 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0  \\
\end{tabular}

\paragraph{Consolidating the Logic Functions: }
$$h_0 = (!x_1) \cdot x_0$$
$$h_1 = 0$$
$$h_2 = x_1 \cdot !x_0$$
$$h_3 = !x_1 \cdot x_0$$
$$h_4 = x_0$$
$$h_5 = x_1 | x_0$$
$$h_6 = !x_1$$

\paragraph{Verilog Code: }
\begin{lstlisting}
module seg7(SW, HEX0)
   input[1:0] X;
   output[6:0] HEX0;

   assign HEX0[0] = ~SW[1] & SW[0];
   // etc.

endmodule
\end{lstlisting}

\paragraph{Implementation Example: }
Designa  circuit with 4 inputs $a, b, c, d$ and $s$.
   if s = 0, show $a+b$ on 7-seg display
   if s = 1, show $c+d$ on 7-seg display

$${a, b} \to mux_{2 bit * 2 inputs} \to fulladd_{cin = 0} \to HEXO \to output$$

\begin{itemize}
\item The carry in digit to the full adder is 0
\item The carry out from the full adder is the most significant digit of the HEXO input.
\item Honestly you could just use a half adder because you don't need a carry-in.
$C_{out} = xy$, $Sum = x \oplus y$
\end{itemize}

\paragraph{Cool XOR Fact: } $\oplus$ returns 1 if the number of true inputs is ODD.

\section{FPGA's}
Can do anything.
\begin{itemize}
\item Field programmable gate arrays: Programmable in the field (i.e. not in the factory necessarily).
\item 2-D array of programmable blocks.
\item Blocks contain lookup tables (LUT)
\item Any two input LUT can be programmed for any two-input logic functions.
\item More complex logic comes out when you connect the LUTS - this is what Quartus does.
\end{itemize}

\paragraph{How to encode any two-input thing}
Let there be 4 sRAM bits $p, q, r, s$. Let the inputs be $a, b$.

$${p, q} \to mux_{a1} \to x$$
$${r, s} \to mux_{a1} \to y$$
Where $x, y$ are itermediate variables.

$${x, y} \to mux_{b} \to output$$

Therefore it takes 4 ram cells for a 2-input LUT. $$n_{ramcells} = 2^{inputs}$$

There are 85,000 6-LUTS on lab chips.

\chapter{Karnaugh Maps}
\section{Motivation}
Creating boolean functions to get what you need done is confusing and unlikely to lead to an optimal solution
when there are many variables.

Karnaugh maps are a tool for expressing your truth tables in such a way that makes getting optimal solutions easier
with many variables.

\paragraph{Example 2x2 Karnaugh Map}
\begin{tabular}{l|cc}
& $0$ & $1$ \\
\hline
0 & a & b \\
1 & c & d \\
\end{tabular}

\section{Review of Terminology}

\begin{itemize}
\item \textbf{Implicant:} Any product term for which the function is true (think 'implies' logic is 1)
\item \textbf{Cover:} A set of implicants that covers all 1's of the function.
\item \textbf{Prime implicant:} Any implicant that, if we delete a literal, is no longer an implicant (largest
   groups of ones in the K-map)
\item \textbf{Essential prime implicant:} Prime implicant that covers a 1 covered by no other prime implicant.
\item \textbf{Min-cost cover:}
\item \textbf{Cost:}
\end{itemize}

\paragraph{Example: }
\begin{tabular}{l|cccc}
& $00$ & $01$ & $11$ & $10$   \\
\hline
0 & 1 & 1 & 1 & 1 \\
1 & 1 & 0 & 0 & 0 \\
\end{tabular}

Let the left column be the $z$ column and the top be products of $x, y$.

List of implicants:
\begin{enumerate}
\item $\bar{z}$
\item $\bar{x} \bar{y}$
\item $\bar{x} \bar{z}$
\item $y\bar{z}$
\item $x\bar{z}$
\item $\bar{y}\bar{z}$
\item $m_{0, 1, 2, 4, 5}$
\end{enumerate}

Prime Implicants: Largest group of ones in cardinal maps...

\paragraph{Cost Defininition: } $n_{gates} + n_{inputs}$

\section{Procedure for Minimum Cost Cover}
\begin{itemize}
\item Find essential prime implicants and include in cover
\item Select additional prime implicants to include in the cover until all 1's are covered.
\end{itemize}

\section{5 Variable Karnaugh Map}
Use two 4-variable K-Maps. One for case where $x_5 = 0$, other for $x_5 = 1$.
Min-term indexing goes by the binary representation of $x_{0-n}$ where $x_n$ is the LEAST significant bit.

\chapter{Storage Elements}
\section{Introduction}
Until now, the values coming in have dependend on the state (high or low) of the input
wires to the circuit. There's another option where the inputs dependent on past states
of the circuit.

\paragraph{Storage elements } represent a \textbf{state} of a circuit. When inputs
change, new inputs either leave circuit in the same state or change the state. These
circuits are called \textbf{sequential} circuits. Memory elements can be created
with logic gates.

\section{RS Latches}
\begin{figure}[h]
\centering
\includegraphics[width=0.7\textwidth]{../media/basicLatch.png}
\caption{Basic Latch}
\label{latch-basic}
\end{figure}
\subsection{Behavior}
You use $S$ to set the output $Q_a$ to $1$ and $R$ to set $Q_a$ to $0$.

\begin{tabular}{ll|ll}
$S$ & $R$ & $Q_a$ & $Q_b$ \\
\hline
0 & 0 & No change &  \\
0 & 1 & 0 & 1 \\
1 & 0 & 1 & 0 \\
1 & 1 & 0 & 0 \\
\end{tabular}

$S$ functions as the 'set' signal.

\section{Gated RS Latch}
Add an and gate to the inputs so that you can only enter signals to the latch when
the $clk$ signal is $1$.

\subsection{Synchronous Reset}
This is when you can only use the reset when the clock is at 1 (basically you just
AND the $D$ and the $R_n$ for an `active low' reset). Reset behavior is synchronized to the rising edge.

\subsection{Behavior}
Same as an RS latch, but you can only send $R$ and $S$ signals when the $clk$ is logic $1$.

\section{Gated D Latch}
Also called `Transparent Latch' or `Level-Sensitive Latch'.

\subsection{Behavior: } When the clock is $1$, then $Q = D$. $Q$ changes as $D$ changes
and then when the clock is turned back to $0$, then $Q$ persists in it's last state.

\section{D Flip-Flops}
\paragraph{Symbol: } Same as the D Latch, but there's a triangle instead of $clk$. If
it's a \textbf{negative edge} triggered flip-flop, the symbol has a bubble next to the
clock. \textbf{Positive edge} appears to be the default.

\paragraph{Edge-Triggered Flip Flop: } The flip flop only changes when the clock is
on a rising edge or a falling edge.

\subsection{Master-Slave Flip Flop}
You connect a master D-Latch to a slave D-Latch. The clock signals of one is the inverse
of the clock symbol going into the other one.

This setup yields a system where you can only change the value of $Q$ for the slave ($Q_s$)
on a rising/falling edge.

\subsection{Behavior} On rising or falling clock edge, the value of $D$ is stored and
appears in $Q$.

\paragraph{Work-Through demonstration: } Let's say you have the inverted clock going
to the slave. When you're in logic 1 for the clock, the master is in \textbf{transparent}
mode. $Q_m = D$. When you switch, the value of the master is stuck and the value of the
slave is set to $Q_m$. You can't reset the slave value after the transition because the
\textbf{opaque} mode of the master.

Pretty cool property!

\subsection{Why it's Useful}

You can put these in the middle of circuits to save values. Then, you can re-inject inputs
while you wait for the last half of the circuit to finish processing. It's like splitting
the circuit into two pieces that can run on different elements simultaneously.

This is a bit of a dumb way to think about it, but that's the general idea behind how
they are actually used.

\section{T Flip-Flop}
Let's take a D Flip Flop component and loop the value of $Q$ and $\bar{Q}$ back to the
input $D$. Let's make $T$ the new input. $T$ switches the input of $D$ between $Q$ and
$\bar{Q}$.

% \section{Flip-Flop Reset/Preset}

% \section{Summary of Objects}

\section{Verilog Implementations}
\subsection{Gated D-Latch}
\begin{lstlisting}
module D_Latch (D, clock, Q, Qb);
   input D, clock;
   output reg Q, Qb; // `reg` means it's an always block

   always@(D,clock) //defining a block that's sensitive to changes in Q and D.
   begin
      if(clock==1'b1)
      begin // need this begin because you're doing two things in the if block.
         Q = D;
         Qb = ~D;
      end // begin and end function like curly braces in C/C++/Java
   end //if clock == 0'b1, then verilog maintains previous values.

endmodule
\end{lstlisting}

\subsection{Edge-Triggered Flip Flop}
\begin{lstlisting}
module D_ft(D, clock, Q, Qb)
   input D, clock;
   output reg Q, Qb;

   // Always blocks tell you what you need to
   always@(posedge clock) // This means you execute this on the positive edge (posedge is a keyword for that)
   begin
      Q <= D; // use '<=' for describing flip flops.
      Qb <= ~D; // we may get to why in this course but for now it's just a thing...
   end
endmodule
\end{lstlisting}

\subsection{Synchronous Reset (Active Low)}
\begin{lstlisting}
always@(popsedge clock)
begin
   if(resetn == 1'b0)
   begin
      Q <= 1'b0;
      Qb <= 1'b1;
   end
   else
   begin
      Q <= D;
      Qb <= ~D;
   end
end

endmodule;

\end{lstlisting}

\chapter{Finite State Machine}
\section{Review}
A finite state machine (FSM) is an object that changes it properties (outputs)
based on inputs over time. For example, a human could be modeled as a state machine
where the input is water over time and the output is the need to go to the bathroom.
\textbf{Sequential circuits} are FSM's.

\subsection{State Diagrams}
\paragraph{Example: } $w$ can be $0, 1$. We are trying to find when $w$ has gone
$1 \to 0 \to 1$.
\paragraph{Solution: } We can use a shift register to get all
the sequential bits of $w$ in, then we use a simple logical expression on the outputs
$w_0 \dot \bar{w_1} \dot w_2$.

\paragraph{One-Hot Encoding: } When only one of your bits is one. \textbf{one cold}
is the opposite.

\subsection{Lmao what is an always block actually}
\begin{lstlisting}
always@(A, B, C)
begin

end
\end{lstlisting}
$A, B, C$ are in the sensitivity list, the code inside is `sensitive' to them so
as they change the internal block is fired. You can only use \textbf{if} statements
in here.

\subsection{Case Statements}
Same as in pretty much all other programming languages.
\begin{lstlisting}
case(A)
   value1:
      do_something;
   value2:
      do_something_else;
   value3: // multiple lines
      begin
         do_something;
         do_something more;
      end
   default:
      default_behavior;
endcase
\end{lstlisting}

% \subsection{State Machine Diagrams and Sequantial Diagrams}

\subsection{Case Statements for State Machines}
Quick example:
\begin{lstlisting}
module FSM(input w, clock, resetn, output z);
   reg[1:0]y, Y;
   parameter A = 2'b0, B = 2'b01, C = 2'b10, D = 2'b11;
   //state table
   always@(w, y) begin
      case(y) begin
         A: begin
            if(W)
               Y = B;
            else
               Y = A;
         end
         B: begin
            if(w)
               Y = B;
            else
               Y = C;
         end
      endcase
   end

   always@(posedge clk) begin
      if(!resetn)
         y <= A;
      else
         y <= Y;
   end

   assign z = (y == D);

endmodule
\end{lstlisting}
\begin{itemize}
\item \textit{parameter} lets you define constants.
\end{itemize}

\chapter{Introduction to Microprocessors}
\section{Computer Organization}
\paragraph{A computer } can read, write, and process data. In order to do so, it has the following main parts:
\begin{enumerate}
\item Input/Output Devices
\item Memory
\item Processor (includes Arithmetic Logic Unit and Control Unit)
\end{enumerate}
All of these are connected through an \textbf{interconnection network}.
\subsection{Memory Unit}
The memory unit can be broken into three main pieces. Overall, it functions to \textbf{store programs} and \textbf{data}.
\subsubsection{Primary Memory}
\begin{itemize}
\item Stores programs
\item Relatively fast, called `main memory'
\item Made of a collection of \textbf{bit registers}
\end{itemize}
The bit registers in memory are read and written in \textbf{WORDS}. Each word has its own address (consecuitive numbers) and a standardized number
of bits.

\subsubsection{Cache}
\begin{itemize}
\item Smaller, faster RAM unit (RAM = Random Access Memory, all can be accessed at the same speed).
\item Holds current parts of a program.
\item Packaged with the processor $\to$ faster to access information from here than from memory.
\end{itemize}

\subsubsection{Secondary Storage}
Basically just external drives.

\subsection{Arithmetic Logic Unit (ALU)}
Most operations are executed here ($+, -, /, \cdot, \leq, \geq, >, <$). Operands are passed here via \textbf{registers}. Registers are
1 word long and are very fast to access.

\subsection{Control Unit}
Coordinates the rest of the units. Usually distributed throughout the compter. The following main types of operations are coordinated by this unit:
\begin{enumerate}
\item Storing information in memory as programs and data.
\item Moving information to memory for the ALU to process.
\item Moving processed information to the output unit.
\end{enumerate}

\chapter{Basic Concepts in Microprocessors}
\section{Basic Concepts}
\lstset{frame=tb,
  language=verilog,
  aboveskip=3mm,
  belowskip=3mm,
  showstringspaces=false,
  columns=flexible,
  basicstyle={\small\ttfamily},
  numbers=none,
  numberstyle=\tiny\color{gray},
  keywordstyle=\color{blue},
  commentstyle=\color{dkgreen},
  stringstyle=\color{mauve},
  breaklines=true,
  breakatwhitespace=true,
  tabsize=3
}

\begin{lstlisting}
LOAD     R2, LOC     // Copies data from main memory into a register.
ADD      R4, R2, R3  // R4 = R2 + R3 (contents)
STORE    R4, LOC     // Copies data from a REGISTER to main memory.

MOVE     R2, R4      // Copy contents of R4 to R2
CLEAR    R2          // Set contents of R2 to be 0
ADD      R2, R2, R4  // R2 = R2 + R4
SUB // Same as add but subtraction
MULTIPLY
DIVIDE

AND      R4, R2, R3  // R4 = R2 & R3
OR
NOT
\end{lstlisting}

The processor's \textbf{PROGRAM COUNTER} (PC) holds the address of the next instruction. Each instruction is 1 word in RISC computers.

\section{Memory Locations and Addresses}
1 cell is 1 bit, and n cells is 1 word. Memory is a collection of words, usually from 16-64.
\paragraph{Address spaces: } The possible addresses in a $k$-bit address space range from $0\to 2^{k}-1$
\paragraph{Byte-addressable memory } indexes each byte (8 bits) with an integer $0, 1, 2... n$. Therefore, in a 32-bit word system,
the address of each word is $0, 4, 8, 12, ...$ in byte addressible memory.

\textbf{Big endian} means that the lower byte address has the more significant digit while \textbf{little endian} holds the oppoiste.

\subsection{Memory Operations}
READ and WRITE are the main operations.

\begin{itemize}
\item READing copies the contents of a memory location to a processor register. This is done by specifying
the address in memory that the processor wants to read.
\item WRITing involves copying the contents of a processor register to a particular
place in memory. The process sends the address it wishes to write to and the data it wants to write there.
\end{itemize}

\section{Instruction Sequencing}
There are 4 operations needed for running a computer program:
\begin{enumerate}
\item Data transfers between memory and process (READ and WRITE)
\item Arithmetic and logic operators
\item Program sequencing and control (branching, subroutines, etc.)
\item Input and Output
\end{enumerate}

\subsection{RISC and CISC Instructions}
\paragraph{RISC: } Each instruction is 1 word long. All arguments must be in registers already.
\paragraph{CISC: } Each instruction can be $\geq$ 1 word long. This enables more complex operations.

\section{Branching}
So far we have talked about \textbf{straight line sequencing}. Instructions are executed in the exact order they are written. But what
if we want to loop?

\begin{lstlisting}
// Some computation
BGT      R4, R5, LOOP      // Go to LOOP if R4 > R5
// Stuff to be executed if R4 <= R5...

LOOP:
   // To be executed if R4 > R5

// SIDE NOTE: This is how you use constants:
SUBTRACT R2, R2, #1 // R2 = R2 - 1
\end{lstlisting}

\section{Addressing Modes}
% So far we have used register modes ($R2$) and absolute modes ($#1$).
A register holding the address of some information in memory is a \textbf{pointer}. Using pointers is called
the \textit{indirect addressing mode}.
\begin{lstlisting}
LOAD     R2, R5         // Loads the stuff from the MEMORY ADDRESS that R5 holds into R2.
MOVE     R2, R5         // Puts the IMMEDIATE VALUE held in R5 into R2.
MOVE     R2, #300       // R2 = 300;
CLEAR    R2             // CLEARS R2 to 0's.

ADD      R4, R0, #200   // R0 usually holds 0's. This what MOVE really does.
\end{lstlisting}

\paragraph{Index mode } of addressing is when you use an address register to hold the address of the first word in a list.
\begin{lstlisting}
// Memory address is equal to some value X (let's say address #96 in memory) plus a register value at Ri
X(Ri) // This is how you address that memory address.
\end{lstlisting}

\section{More on Assembly}
\begin{lstlisting}
TWENTY   EQU   20 // Whenever the assembler sees `TWENTY' it will be replaced by 20.

ORIGIN   100      // Inser this at the beginning of a block to specify that code below should be placed in memory starting at address #100

SUM   :  Reserve  4  // 4-byte space reserved @ address 100
N     :  Dataword    // N = #150 @ address 204
End // ends the program.

%10110101 // how to specify numbers in binary
0x5f      // hot to specify number in hex
\end{lstlisting}

\section{Stacks}
Same common datastructure we ran into before in CSC190. Only one end can be read/added to, and it's LIFO (last in, first out).

\paragraph{The Stack Pointer (SP)} points to the address of the end of the stack (Processor stack). Common practice: stack grows in direction of
\textit{decreasing memory addresses}.
The push operation works as follows (pushing word in $R_i$):
\begin{lstlisting}
SUB         SP, SP, #4     // Decrementing stack pointer by 4 bytes (1 word).
STORE       Ri, SP
// Now the pop operator:
LOAD        Ri, SP
ADD         SP, SP, #4
\end{lstlisting}

\section{Subroutines}
Same as a function. Uses branching, but it knows that it has to return to where it was called from. We use the \textbf{RETURN} command
to return to the calling place. The address of the calling place is stored in the \textbf{LINK REGISTER}.

\begin{lstlisting}
CALL        FUNCNAME       // Stores current PROGRAM COUNTER in LINK REGISTER, branches to subroutine.
// .. some code ..
FUNCNAME:
   // .. some code ..
   RETURN                  // Branches back to address stored in LINK REGISTER
\end{lstlisting}

\subsection{Subroutine Nesting}
If you call a function in a function, the LINK REGISTER can only hold one address at a time. Since we need LIFO structure to
tell us where to branch back to at each successive return, we use the \textbf{PROCESSOR STACK} to store the further addresses.

\paragraph{Process for calling a nested function: }
\begin{enumerate}
\item Return address in LR $\to$ PROCESSOR STACK @SP.
\item Store current address in LR and branch to the next function.
\item When you return from the nested function, transfer the original LR pointer back from PROCESSOR STACK @SP.
\item Return as normal to address in LR when you're done with the original subroutine.
\end{enumerate}

\subsection{Parameter Passing}
This can be done with registers or via the \textbf{PROCESSOR STACK}. Here are the steps for the PROCESSOR STACK approach:
\begin{enumerate}
\item Push the arguments you want to pass to the stack in the caller.
\item Once in the subroutine, save the contents of current registers to the stack to preserve the state of the calling program.
\item Use an offset equal to the number of SAVED REGISTERS to access passed variables.
\item Carry out the subroutine.
\item Restore the disturbed registers from the stack (pop them off).
\item Branch back to the address of the caller and re-establish the SP to what it was originally.
\end{enumerate}

\subsection{Stack Frame}
\paragraph{Definition: } The Stack Frame is the space allocated to a subroutine when it is called. It is useful to
have a \textbf{FRAME POINTER} that points to just above the PASSED PARAMETERS (unlike the STACK POINTER SP that points
to the actual top of the stack that also holds the saved registers).

\paragraph{FRAME POINTER FP } is a constant for the duration of the subroutine program. It is equal to the STACK POINTER SP
at the beginning of the subroutine call.

\section{Flags and Conditionals}
You pretty much always want to branch/call a subroutine on a conditional. Here's who they work:
\subsection{Comparisons}
\textbf{CMP R2, R1} lets you compare the values of two things. It performs the operation $R2 - R1$ and stores attributes of the result in global \textbf{FLAGS}
\subsection{Flags}
Flags are values you can use to branch. They store attributes of the previous comparison or operation.
\begin{enumerate}
\item $N$: If the result was negative.
\item $Z$: If the result was zero.
\item $C$: If the result of an unsigned operation overflows.
\item $V$: If the result of a signed operation overflows.
\end{enumerate}

The following Assembly directives make use of the previous comparison's flags:
\begin{enumerate}
\item $BEQ$: If the previous comparison yielded equality.
\item $BLT$: If the previous comparison yielded less than.
\item $BGT$: If the previous comparison yielded greater than.
\end{enumerate}

\chapter{IO Devices}
You access IO devices in the same way you might access regular registers. The \textbf{device interface} gives you a few registers that
allow you to communicate:
\begin{enumerate}
\item Data
\item Status
\item Control
\end{enumerate}

\section{Program Control IO}
You use a program called a \textbf{Program Control Interface} to write and control an IO device.

Because the processor, input, and output devices may work at different rates, you need to wait for a response to any signal you
send to one to make sure it's ready for the next one. These are called \textbf{STATUS FLAGS}, and reading them is called \textbf{POLLING}.

\section{Interrupts}
You can use the infinite loop approach where you just keep POLLING the STATUS FLAG of an IO device until it's ready. That takes a lot of
compute power and you can't do anything during the wait time, which is a problem.

\paragraph{INTERRUPT SERVICE ROUTINE } is called by an interrupt signal from an IO device. Here is the processor's steps for dealing with one.
\begin{enumerate}
\item The processor finishes instruction $i$ that it is in the middle of.
\item The processor branches to the INTERRUPT ROUTINE. PC $\to$ PROCESSOR STACK.
\item The INTERRUPT ROUTINE is executed.
\item The PC is restored from the PROCESSOR STACK.
\end{enumerate}

\subsection{Notes on SUBROUTINE INTERRUPT IMPLEMENTATION: }
At the beginning of the subroutine, the processor must send an \textbf{INTERRUPT ACKNOWLEDGE} make sure that, when the subroutine RETURNS,
an infinite loop does not occur. Alternatively, the successful execution of the subroutine can implicitly notify the IO device.

\paragraph{REGISTERS MUST BE RESTORED } because you don't know when the interrupt subroutine will be executed. It could be in the middle of another
very sensitive subroutine.

\subsection{Enable and Disabling Interrupts}
Sometimes you don't want to branch away from the main progam. Therefore, the processor has some STATUS REGISTERS PS that have a bit INTERRUPT INABLE IE
that, when set to 0, disable interrupts.

\textbf{You must set this } to 0 while inside the subroutine to avoid an infinite loop..

\paragraph{IO MODE } bit in the control interface of the IO device can also allow you to set whether it sends interrupts or not.

\subsection{Process for a Single Device Interrupt Call}
\begin{enumerate}
\item Device raises interrupt
\item Processor branches to the interrupt subroutine
\item STATUS REGISTER PS is saved to the stack, along with the PROGRAM COUNTER PC.
\item STATUS REGISTER PS has INTERRUPT ENABLE IE that is set to 0.
\item Subroutine runs.
\item STATUS REGISTER PS is restored from the saved version.
\end{enumerate}

\section{Multiple Device Interrupts}
The above system works fine when you just have one interrupt at a time or one device performing the interrupts.

\subsection{Approach One: Naïve Polling}
You can just do the same thing as before, just executing the interrupts in the order you poll them if they happen to come at the same time. However,
polling takes time.

\subsection{Vectored Inputs}
If you allow the interruptor to send a message along with their interrupt, you can have code in the processor that tells it how to
interpret the signal.

\paragraph{INTERRUPT VECTOR TABLE } is stored (usually in the lowest address range). The information in a vectored interrupt contains the
address of one of the vectors in that table. The contents of that vector in the table is the address of the interrupt subroutine.

\subsection{Interrupt Nesting}
If an interrupt comes in while executing another interrupt's subroutine, there's a chance that it will be of higher priority. Therefore,
we need an interrupt priority system.

\paragraph{PROCESSOR PRIORITY } is the priority of the current process. Only interrupts with a higher priority are executed. Priority is
communicated in the interrupt vector.

\section{Processor Control Register}
We already know that the INTERRUPT ENABLE IE bit is in the PROCESSOR STATUS register which is one of the PROCESSOR CONTROL REGISTERS.

IPS is where PS is saved automatically at the start of an interrupt. PS is autorestored from here at the end.

IENABLE register enables device specific INTERRUPT ENABLE bits.

IPENDING register shows which interrupts are active.

Since all registers are 1 word long, you can generally have 32 IO devices.

In order to read and write from PROCESSOR CONTROL REGISTERS, you treat them like regular registers.

\chapter{Closing Remarks}
\section{Multiplexer Synethesis}
You can make any logical circuit out of a bunch of multiplexers. The naïve aproach is to have the actual inputs of the
multiplexer be constants and the selector inputs be your inputs to the function.

\paragraph{Shannon's Expansion } allows you to further simplify your naïve multiplexer layout:
$$f(w_1, ... , w_n) = \bar{w}_1\cdot f(0, w_2, ..., w_n) + w_1 \cdot f(1, w_2, ..., w_n)$$

\section{Timing Considerations for Flip Flop Circuits}
We need to know $F_{max}$, the maximum frequency at which we can run our clocks when using a flip flop.

\paragraph{Hold time violation } is
\paragraph{Timing parameters }
\begin{itemize}
\item $t_{su}$: \textbf{Set up time} while data D must be stable for a D-latch or D-fip flop.
\item $t_h$: Data must stay stable during \textbf{hold time}
\item $t_{cQ}$: Time from \textbf{clock signal to Q} for a flip flop.
\end{itemize}

\paragraph{To get clock's $T_{min}$}, you add up the maximum required time for a signal to propagate through the circuit.

\subsection{Clock Skew}
Clock signal might not arrive at different flip flops at the same time.

\paragraph{$t_{skew}$} = time of arrival at sink - time of arrival at source.

If skew time is positive, you can have a higher $F_max$. Negative leads to lower $F_max$.

\subsection{Process for Timing Analysis}
\begin{enumerate}
\item Calculate longest path the signal must traverse during a clock cycle. $T_{min} \geq T_{longest_path}$
\item Calculate hold time violation (which is the time the data must be constant for the latch to `save' the data). `'
\item Calculate time violation:
\end{enumerate}

\end{document}


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\title{Document X}
\author{Jo Student}
\affiliation{PHYS 220, Schmid College of Science and Technology, Chapman University}
\date{\today}

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&= -\frac{\hbar^2}{2m}\nabla^2\psi(x,t) + V(x)\psi(x,t). \nonumber
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\documentclass[]{AVSSimReportMemo}

\newcommand{\ModuleName}{LowPassFilterTorqueCommand}
\newcommand{\subject}{Low Pass Module on ADCS Control Torque Command}
\newcommand{\status}{Initial documentation.}
\newcommand{\preparer}{H. Schaub}
\newcommand{\summary}{This module provides a low-pass filter that operates on the ADCS control torque vector.     }

\begin{document}

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{\bfseries Rev}: & {\bfseries Change Description} & {\bfseries By} \\
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Draft & Initial Documenation & H. Schaub \\
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\section{Introduction}
A low-pass filter module provides the ability to apply a frequency based filter to the ADCS control torque vector $\bm L_{r}$.  The module has the ability to be individually reset, separate from any reset on the ADCS control modules.  The cut-off frequency is given by $\omega_{c}$, while the filter time step is given by $h$.

\section{Initialization}
Prior to using the module, the filter time step and 1st order filter frequency cut-off value must be set.
\begin{gather*}
{\tt Config->h} \\
 {\tt Config->wc}
\end{gather*}

\section{Algorithm}
Since the shown mappings between the Laplace domain and the $Z$-domain
are approximate, some frequency warping will occur.  If a continuous
filter design has a critical frequency $\omega_{c}$, then the digital
implementation might have a slightly different critical frequency.
Franklin in Reference~\citenum{franklin1} compares the continuous and
digital filter performances by studying the half-power point.  This
leads to the following relationship between the continuous time
critical filter frequency $\omega_{c}$ and the digital filter
frequency $\hat\omega$:
\begin{equation}
	\label{eq:wa}
	\tan \left(\frac{ w_{c} h}{2}\right) = \frac{\hat\omega h}{2}
\end{equation}
where $h=1/f$ is the digital sample time.  Note that $\hat\omega \approx
\omega_{c}$ if the sample frequency is much higher than the critical
filter frequency.

The first-order digital filter formula is given by:
\begin{equation}
		y_{k} = \frac{1}{2+h \omega_{c}}
		\Big[
		y_{k-1} (2-h \omega_{c})  + h \omega_{c} (x_{k} + x_{k-1})
		\Big]
\end{equation}
where $x_{k}$ is the current filter input, and $y_{k}$ is the filtered output.

\section{Output}
The filter module outputs the standard ADCS control torque output structure.  If the original and filtered ADCS control is to be tracked, then the messages should be given unique names.

\bibliographystyle{unsrt}
\bibliography{references}

\end{document}