first cut at import BVI for ethernet buffer

/*
   ../../generated/scripts/importbvi.py
   -o
   AxiEthBuffer.bsv
   -I
   AxiEthBuffer
   -P
   AxiEthBuffer
   -c
   S_AXI_ACLK
   -r
   S_AXI_ARESETN
   -c
   AXI_STR_TXD_ACLK
   -r
   AXI_STR_TXD_ARESETN
   -c
   AXI_STR_TXC_ACLK
   -r
   AXI_STR_TXC_ARESETN
   -c
   AXI_STR_RXD_ACLK
   -r
   AXI_STR_RXD_ARESETN
   -c
   AXI_STR_RXS_ACLK
   -r
   AXI_STR_RXS_ARESETN
   -c
   rx_mac_aclk
   -r
   rx_reset
   -c
   tx_mac_aclk
   -r
   tx_reset
   -r
   PHY_RST_N
   -r
   RESET2PCSPMA
   -r
   RESET2TEMACn
   -c
   GTX_CLK
   -n
   speed_is_10_100
   -f
   S_AXI_2TEMAC
   -n
   RESET2PCSPMA
   -n
   RESET2TEMACn
   cores/nfsume/eth_buf/eth_buf_stub.v
*/

import Clocks::*;
import DefaultValue::*;
import XilinxCells::*;
import GetPut::*;
import AxiBits::*;

(* always_ready, always_enabled *)
interface AxiethbufferAxi;
    method Bit#(32)     str_rxd_data();
    method Bit#(4)     str_rxd_keep();
    method Bit#(1)     str_rxd_last();
    method Action      str_rxd_ready(Bit#(1) v);
    method Bit#(1)     str_rxd_valid();
    method Bit#(32)     str_rxs_data();
    method Bit#(4)     str_rxs_keep();
    method Bit#(1)     str_rxs_last();
    method Action      str_rxs_ready(Bit#(1) v);
    method Bit#(1)     str_rxs_valid();
    method Action      str_txc_tdata(Bit#(32) v);
    method Action      str_txc_tkeep(Bit#(4) v);
    method Action      str_txc_tlast(Bit#(1) v);
    method Bit#(1)     str_txc_tready();
    method Action      str_txc_tvalid(Bit#(1) v);
    method Action      str_txd_tdata(Bit#(32) v);
    method Action      str_txd_tkeep(Bit#(4) v);
    method Action      str_txd_tlast(Bit#(1) v);
    method Bit#(1)     str_txd_tready();
    method Action      str_txd_tvalid(Bit#(1) v);
endinterface
(* always_ready, always_enabled *)
interface AxiethbufferEmac;
    method Action      client_autoneg_int(Bit#(1) v);
    method Action      reset_done_int(Bit#(1) v);
    method Action      rx_dcm_locked_int(Bit#(1) v);
endinterface
(* always_ready, always_enabled *)
(* always_ready, always_enabled *)
interface AxiethbufferMdc;
    method Action      temac(Bit#(1) v);
    method Bit#(1)     top();
endinterface
(* always_ready, always_enabled *)
interface AxiethbufferMdio;
    method Bit#(1)     i_temac();
    method Action      i_top(Bit#(1) v);
    method Action      o_pcspma(Bit#(1) v);
    method Action      o_temac(Bit#(1) v);
    method Bit#(1)     o_top();
    method Action      t_pcspma(Bit#(1) v);
    method Action      t_temac(Bit#(1) v);
    method Bit#(1)     t_top();
endinterface
(* always_ready, always_enabled *)
interface AxiethbufferPause;
    method Bit#(1)     req();
    method Bit#(17)     val();
endinterface
(* always_ready, always_enabled *)
interface AxiethbufferPcspma;
    method Action      status_vector(Bit#(16) v);
endinterface
(* always_ready, always_enabled *)
interface AxiethbufferPhy;
    method Reset     rst_n();
endinterface
(* always_ready, always_enabled *)
interface AxiethbufferRx;
    method Action      axis_mac_tdata(Bit#(8) v);
    method Action      axis_mac_tlast(Bit#(1) v);
    method Action      axis_mac_tuser(Bit#(1) v);
    method Action      axis_mac_tvalid(Bit#(1) v);
    method Action      clk_enable_in(Bit#(1) v);
    method Action      statistics_valid(Bit#(1) v);
    method Action      statistics_vector(Bit#(28) v);
endinterface
(* always_ready, always_enabled *)
interface AxiethbufferS_axi;
    method Action      araddr(Bit#(18) v);
    method Bit#(1)     arready();
    method Action      arvalid(Bit#(1) v);
    method Action      awaddr(Bit#(18) v);
    method Bit#(1)     awready();
    method Action      awvalid(Bit#(1) v);
    method Action      bready(Bit#(1) v);
    method Bit#(2)     bresp();
    method Bit#(1)     bvalid();
    method Bit#(32)     rdata();
    method Action      rready(Bit#(1) v);
    method Bit#(2)     rresp();
    method Bit#(1)     rvalid();
    method Action      wdata(Bit#(32) v);
    method Bit#(1)     wready();
    method Action      wstrb(Bit#(4) v);
    method Action      wvalid(Bit#(1) v);
endinterface
(* always_ready, always_enabled *)
interface AxiethbufferS_axi_2temac;
    method Bit#(12)     araddr();
    method Action      arready(Bit#(1) v);
    method Bit#(1)     arvalid();
    method Bit#(12)     awaddr();
    method Action      awready(Bit#(1) v);
    method Bit#(1)     awvalid();
    method Bit#(1)     bready();
    method Action      bresp(Bit#(2) v);
    method Action      bvalid(Bit#(1) v);
    method Action      rdata(Bit#(32) v);
    method Bit#(1)     rready();
    method Action      rresp(Bit#(2) v);
    method Action      rvalid(Bit#(1) v);
    method Bit#(32)     wdata();
    method Action      wready(Bit#(1) v);
    method Bit#(1)     wvalid();
endinterface
(* always_ready, always_enabled *)
interface AxiethbufferTx;
    method Bit#(8)     axis_mac_tdata();
    method Bit#(1)     axis_mac_tlast();
    method Action      axis_mac_tready(Bit#(1) v);
    method Bit#(1)     axis_mac_tuser();
    method Bit#(1)     axis_mac_tvalid();
    method Bit#(9)     ifg_delay();
endinterface
(* always_ready, always_enabled *)
interface AxiEthBuffer;
    interface AxiethbufferAxi     axi;
    interface AxiethbufferEmac     emac;
    method Bit#(1)     interrupt();
    interface AxiethbufferMdc     mdc;
    interface AxiethbufferMdio     mdio;
    interface AxiethbufferPause     pause;
    interface AxiethbufferPcspma     pcspma;
    interface AxiethbufferPhy     phy;
    method Reset     reset2pcspma();
    method Reset     reset2temacn();
    interface AxiethbufferRx     rx;
    interface AxiethbufferS_axi_2temac     s_axi_2temac;
    interface AxiethbufferS_axi     s_axi;
    method Action      speed_is_10_100(Bit#(1) v);
    interface AxiethbufferTx     tx;
endinterface
import "BVI" eth_buf(INTERRUPT, =
module mkAxiEthBuffer#(Clock axi_str_rxd_aclk, Clock axi_str_rxs_aclk, Clock axi_str_txc_aclk, Clock axi_str_txd_aclk, Clock gtx_clk, Clock rx_mac_aclk, Clock s_axi_aclk, Clock tx_mac_aclk, Reset axi_str_rxd_aclk_reset, Reset axi_str_rxd_aresetn, Reset axi_str_rxs_aclk_reset, Reset axi_str_rxs_aresetn, Reset axi_str_txc_aclk_reset, Reset axi_str_txc_aresetn, Reset axi_str_txd_aclk_reset, Reset axi_str_txd_aresetn, Reset gtx_clk_reset, Reset rx_mac_aclk_reset, Reset rx_reset, Reset s_axi_aclk_reset, Reset s_axi_aresetn, Reset tx_mac_aclk_reset, Reset tx_reset)(AxiEthBuffer);
    default_clock clk();
    default_reset rst();
        input_clock axi_str_rxd_aclk(AXI_STR_RXD_ACLK) = axi_str_rxd_aclk;
        input_reset axi_str_rxd_aclk_reset() = axi_str_rxd_aclk_reset; /* from clock*/
        input_reset axi_str_rxd_aresetn(AXI_STR_RXD_ARESETN) = axi_str_rxd_aresetn;
        input_clock axi_str_rxs_aclk(AXI_STR_RXS_ACLK) = axi_str_rxs_aclk;
        input_reset axi_str_rxs_aclk_reset() = axi_str_rxs_aclk_reset; /* from clock*/
        input_reset axi_str_rxs_aresetn(AXI_STR_RXS_ARESETN) = axi_str_rxs_aresetn;
        input_clock axi_str_txc_aclk(AXI_STR_TXC_ACLK) = axi_str_txc_aclk;
        input_reset axi_str_txc_aclk_reset() = axi_str_txc_aclk_reset; /* from clock*/
        input_reset axi_str_txc_aresetn(AXI_STR_TXC_ARESETN) = axi_str_txc_aresetn;
        input_clock axi_str_txd_aclk(AXI_STR_TXD_ACLK) = axi_str_txd_aclk;
        input_reset axi_str_txd_aclk_reset() = axi_str_txd_aclk_reset; /* from clock*/
        input_reset axi_str_txd_aresetn(AXI_STR_TXD_ARESETN) = axi_str_txd_aresetn;
        input_clock gtx_clk(GTX_CLK) = gtx_clk;
        input_reset gtx_clk_reset() = gtx_clk_reset; /* from clock*/
        input_clock rx_mac_aclk(rx_mac_aclk) = rx_mac_aclk;
        input_reset rx_mac_aclk_reset() = rx_mac_aclk_reset; /* from clock*/
        input_reset rx_reset(rx_reset) = rx_reset;
        input_clock s_axi_aclk(S_AXI_ACLK) = s_axi_aclk;
        input_reset s_axi_aclk_reset() = s_axi_aclk_reset; /* from clock*/
        input_reset s_axi_aresetn(S_AXI_ARESETN) = s_axi_aresetn;
        input_clock tx_mac_aclk(tx_mac_aclk) = tx_mac_aclk;
        input_reset tx_mac_aclk_reset() = tx_mac_aclk_reset; /* from clock*/
        input_reset tx_reset(tx_reset) = tx_reset;
    interface AxiethbufferAxi     axi;
        method AXI_STR_RXD_DATA str_rxd_data() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset);
        method AXI_STR_RXD_KEEP str_rxd_keep() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset);
        method AXI_STR_RXD_LAST str_rxd_last() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset);
        method str_rxd_ready(AXI_STR_RXD_READY) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset) enable((*inhigh*) EN_AXI_STR_RXD_READY);
        method AXI_STR_RXD_VALID str_rxd_valid() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset);
        method AXI_STR_RXS_DATA str_rxs_data() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset);
        method AXI_STR_RXS_KEEP str_rxs_keep() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset);
        method AXI_STR_RXS_LAST str_rxs_last() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset);
        method str_rxs_ready(AXI_STR_RXS_READY) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset) enable((*inhigh*) EN_AXI_STR_RXS_READY);
        method AXI_STR_RXS_VALID str_rxs_valid() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset);
        method str_txc_tdata(AXI_STR_TXC_TDATA) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset) enable((*inhigh*) EN_AXI_STR_TXC_TDATA);
        method str_txc_tkeep(AXI_STR_TXC_TKEEP) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset) enable((*inhigh*) EN_AXI_STR_TXC_TKEEP);
        method str_txc_tlast(AXI_STR_TXC_TLAST) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset) enable((*inhigh*) EN_AXI_STR_TXC_TLAST);
        method AXI_STR_TXC_TREADY str_txc_tready() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset);
        method str_txc_tvalid(AXI_STR_TXC_TVALID) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset) enable((*inhigh*) EN_AXI_STR_TXC_TVALID);
        method str_txd_tdata(AXI_STR_TXD_TDATA) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset) enable((*inhigh*) EN_AXI_STR_TXD_TDATA);
        method str_txd_tkeep(AXI_STR_TXD_TKEEP) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset) enable((*inhigh*) EN_AXI_STR_TXD_TKEEP);
        method str_txd_tlast(AXI_STR_TXD_TLAST) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset) enable((*inhigh*) EN_AXI_STR_TXD_TLAST);
        method AXI_STR_TXD_TREADY str_txd_tready() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset);
        method str_txd_tvalid(AXI_STR_TXD_TVALID) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aclk_reset) enable((*inhigh*) EN_AXI_STR_TXD_TVALID);
    endinterface
    interface AxiethbufferEmac     emac;
        method client_autoneg_int(EMAC_CLIENT_AUTONEG_INT) enable((*inhigh*) EN_EMAC_CLIENT_AUTONEG_INT);
        method reset_done_int(EMAC_RESET_DONE_INT) enable((*inhigh*) EN_EMAC_RESET_DONE_INT);
        method rx_dcm_locked_int(EMAC_RX_DCM_LOCKED_INT) enable((*inhigh*) EN_EMAC_RX_DCM_LOCKED_INT);
    endinterface
    method INTERRUPT interrupt();
    interface AxiethbufferMdc     mdc;
        method temac(mdc_temac) enable((*inhigh*) EN_mdc_temac);
        method mdc_top top();
    endinterface
    interface AxiethbufferMdio     mdio;
        method mdio_i_temac i_temac();
        method i_top(mdio_i_top) enable((*inhigh*) EN_mdio_i_top);
        method o_pcspma(mdio_o_pcspma) enable((*inhigh*) EN_mdio_o_pcspma);
        method o_temac(mdio_o_temac) enable((*inhigh*) EN_mdio_o_temac);
        method mdio_o_top o_top();
        method t_pcspma(mdio_t_pcspma) enable((*inhigh*) EN_mdio_t_pcspma);
        method t_temac(mdio_t_temac) enable((*inhigh*) EN_mdio_t_temac);
        method mdio_t_top t_top();
    endinterface
    interface AxiethbufferPause     pause;
        method pause_req req();
        method pause_val val();
    endinterface
    interface AxiethbufferPcspma     pcspma;
        method status_vector(PCSPMA_STATUS_VECTOR) enable((*inhigh*) EN_PCSPMA_STATUS_VECTOR);
    endinterface
    interface AxiethbufferPhy     phy;
        output_reset rst_n(PHY_RST_N);
    endinterface
    output_reset reset2pcspma(RESET2PCSPMA);
    output_reset reset2temacn(RESET2TEMACn);
    interface AxiethbufferRx     rx;
        method axis_mac_tdata(rx_axis_mac_tdata) clocked_by (rx_mac_aclk) reset_by (rx_mac_aclk_reset) enable((*inhigh*) EN_rx_axis_mac_tdata);
        method axis_mac_tlast(rx_axis_mac_tlast) clocked_by (rx_mac_aclk) reset_by (rx_mac_aclk_reset) enable((*inhigh*) EN_rx_axis_mac_tlast);
        method axis_mac_tuser(rx_axis_mac_tuser) clocked_by (rx_mac_aclk) reset_by (rx_mac_aclk_reset) enable((*inhigh*) EN_rx_axis_mac_tuser);
        method axis_mac_tvalid(rx_axis_mac_tvalid) clocked_by (rx_mac_aclk) reset_by (rx_mac_aclk_reset) enable((*inhigh*) EN_rx_axis_mac_tvalid);
        method clk_enable_in(rx_CLK_ENABLE_IN) clocked_by (rx_mac_aclk) reset_by (rx_mac_aclk_reset) enable((*inhigh*) EN_rx_CLK_ENABLE_IN);
        method statistics_valid(rx_statistics_valid) clocked_by (rx_mac_aclk) reset_by (rx_mac_aclk_reset) enable((*inhigh*) EN_rx_statistics_valid);
        method statistics_vector(rx_statistics_vector) clocked_by (rx_mac_aclk) reset_by (rx_mac_aclk_reset) enable((*inhigh*) EN_rx_statistics_vector);
    endinterface
    interface AxiethbufferS_axi_2temac     s_axi_2temac;
        method S_AXI_2TEMAC_ARADDR araddr();
        method arready(S_AXI_2TEMAC_ARREADY) enable((*inhigh*) EN_S_AXI_2TEMAC_ARREADY);
        method S_AXI_2TEMAC_ARVALID arvalid();
        method S_AXI_2TEMAC_AWADDR awaddr();
        method awready(S_AXI_2TEMAC_AWREADY) enable((*inhigh*) EN_S_AXI_2TEMAC_AWREADY);
        method S_AXI_2TEMAC_AWVALID awvalid();
        method S_AXI_2TEMAC_BREADY bready();
        method bresp(S_AXI_2TEMAC_BRESP) enable((*inhigh*) EN_S_AXI_2TEMAC_BRESP);
        method bvalid(S_AXI_2TEMAC_BVALID) enable((*inhigh*) EN_S_AXI_2TEMAC_BVALID);
        method rdata(S_AXI_2TEMAC_RDATA) enable((*inhigh*) EN_S_AXI_2TEMAC_RDATA);
        method S_AXI_2TEMAC_RREADY rready();
        method rresp(S_AXI_2TEMAC_RRESP) enable((*inhigh*) EN_S_AXI_2TEMAC_RRESP);
        method rvalid(S_AXI_2TEMAC_RVALID) enable((*inhigh*) EN_S_AXI_2TEMAC_RVALID);
        method S_AXI_2TEMAC_WDATA wdata();
        method wready(S_AXI_2TEMAC_WREADY) enable((*inhigh*) EN_S_AXI_2TEMAC_WREADY);
        method S_AXI_2TEMAC_WVALID wvalid();
    endinterface
    interface AxiethbufferS_axi     s_axi;
        method araddr(S_AXI_ARADDR) clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset) enable((*inhigh*) EN_S_AXI_ARADDR);
        method S_AXI_ARREADY arready() clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset);
        method arvalid(S_AXI_ARVALID) clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset) enable((*inhigh*) EN_S_AXI_ARVALID);
        method awaddr(S_AXI_AWADDR) clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset) enable((*inhigh*) EN_S_AXI_AWADDR);
        method S_AXI_AWREADY awready() clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset);
        method awvalid(S_AXI_AWVALID) clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset) enable((*inhigh*) EN_S_AXI_AWVALID);
        method bready(S_AXI_BREADY) clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset) enable((*inhigh*) EN_S_AXI_BREADY);
        method S_AXI_BRESP bresp() clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset);
        method S_AXI_BVALID bvalid() clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset);
        method S_AXI_RDATA rdata() clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset);
        method rready(S_AXI_RREADY) clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset) enable((*inhigh*) EN_S_AXI_RREADY);
        method S_AXI_RRESP rresp() clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset);
        method S_AXI_RVALID rvalid() clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset);
        method wdata(S_AXI_WDATA) clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset) enable((*inhigh*) EN_S_AXI_WDATA);
        method S_AXI_WREADY wready() clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset);
        method wstrb(S_AXI_WSTRB) clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset) enable((*inhigh*) EN_S_AXI_WSTRB);
        method wvalid(S_AXI_WVALID) clocked_by (s_axi_aclk) reset_by (s_axi_aclk_reset) enable((*inhigh*) EN_S_AXI_WVALID);
    endinterface
    method speed_is_10_100(speed_is_10_100) enable((*inhigh*) EN_speed_is_10_100);
    interface AxiethbufferTx     tx;
        method tx_axis_mac_tdata axis_mac_tdata() clocked_by (tx_mac_aclk) reset_by (tx_mac_aclk_reset);
        method tx_axis_mac_tlast axis_mac_tlast() clocked_by (tx_mac_aclk) reset_by (tx_mac_aclk_reset);
        method axis_mac_tready(tx_axis_mac_tready) clocked_by (tx_mac_aclk) reset_by (tx_mac_aclk_reset) enable((*inhigh*) EN_tx_axis_mac_tready);
        method tx_axis_mac_tuser axis_mac_tuser() clocked_by (tx_mac_aclk) reset_by (tx_mac_aclk_reset);
        method tx_axis_mac_tvalid axis_mac_tvalid() clocked_by (tx_mac_aclk) reset_by (tx_mac_aclk_reset);
        method tx_ifg_delay ifg_delay() clocked_by (tx_mac_aclk) reset_by (tx_mac_aclk_reset);
    endinterface
    schedule (axi.str_rxd_data, axi.str_rxd_keep, axi.str_rxd_last, axi.str_rxd_ready, axi.str_rxd_valid, axi.str_rxs_data, axi.str_rxs_keep, axi.str_rxs_last, axi.str_rxs_ready, axi.str_rxs_valid, axi.str_txc_tdata, axi.str_txc_tkeep, axi.str_txc_tlast, axi.str_txc_tready, axi.str_txc_tvalid, axi.str_txd_tdata, axi.str_txd_tkeep, axi.str_txd_tlast, axi.str_txd_tready, axi.str_txd_tvalid, emac.client_autoneg_int, emac.reset_done_int, emac.rx_dcm_locked_int, interrupt, mdc.temac, mdc.top, mdio.i_temac, mdio.i_top, mdio.o_pcspma, mdio.o_temac, mdio.o_top, mdio.t_pcspma, mdio.t_temac, mdio.t_top, pause.req, pause.val, pcspma.status_vector, rx.axis_mac_tdata, rx.axis_mac_tlast, rx.axis_mac_tuser, rx.axis_mac_tvalid, rx.clk_enable_in, rx.statistics_valid, rx.statistics_vector, s_axi_2temac.araddr, s_axi_2temac.arready, s_axi_2temac.arvalid, s_axi_2temac.awaddr, s_axi_2temac.awready, s_axi_2temac.awvalid, s_axi_2temac.bready, s_axi_2temac.bresp, s_axi_2temac.bvalid, s_axi_2temac.rdata, s_axi_2temac.rready, s_axi_2temac.rresp, s_axi_2temac.rvalid, s_axi_2temac.wdata, s_axi_2temac.wready, s_axi_2temac.wvalid, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wstrb, s_axi.wvalid, speed_is_10_100, tx.axis_mac_tdata, tx.axis_mac_tlast, tx.axis_mac_tready, tx.axis_mac_tuser, tx.axis_mac_tvalid, tx.ifg_delay) CF (axi.str_rxd_data, axi.str_rxd_keep, axi.str_rxd_last, axi.str_rxd_ready, axi.str_rxd_valid, axi.str_rxs_data, axi.str_rxs_keep, axi.str_rxs_last, axi.str_rxs_ready, axi.str_rxs_valid, axi.str_txc_tdata, axi.str_txc_tkeep, axi.str_txc_tlast, axi.str_txc_tready, axi.str_txc_tvalid, axi.str_txd_tdata, axi.str_txd_tkeep, axi.str_txd_tlast, axi.str_txd_tready, axi.str_txd_tvalid, emac.client_autoneg_int, emac.reset_done_int, emac.rx_dcm_locked_int, interrupt, mdc.temac, mdc.top, mdio.i_temac, mdio.i_top, mdio.o_pcspma, mdio.o_temac, mdio.o_top, mdio.t_pcspma, mdio.t_temac, mdio.t_top, pause.req, pause.val, pcspma.status_vector, rx.axis_mac_tdata, rx.axis_mac_tlast, rx.axis_mac_tuser, rx.axis_mac_tvalid, rx.clk_enable_in, rx.statistics_valid, rx.statistics_vector, s_axi_2temac.araddr, s_axi_2temac.arready, s_axi_2temac.arvalid, s_axi_2temac.awaddr, s_axi_2temac.awready, s_axi_2temac.awvalid, s_axi_2temac.bready, s_axi_2temac.bresp, s_axi_2temac.bvalid, s_axi_2temac.rdata, s_axi_2temac.rready, s_axi_2temac.rresp, s_axi_2temac.rvalid, s_axi_2temac.wdata, s_axi_2temac.wready, s_axi_2temac.wvalid, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wstrb, s_axi.wvalid, speed_is_10_100, tx.axis_mac_tdata, tx.axis_mac_tlast, tx.axis_mac_tready, tx.axis_mac_tuser, tx.axis_mac_tvalid, tx.ifg_delay);
endmodule

error: pathspec 'tests/spikehw/AxiEthBuffer.bsv' did not match any file(s) known to git


print trace from csail-csg/recycle-bsv-lib

// Copyright (c) 2016 Massachusetts Institute of Technology

// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

package PrintTrace;

// XXX: For now export everything
// export printTrace;
// export fprintTrace;
// export printTraceM;
// export fprintTraceM;

import ClientServer::*;
import FIFO::*;
import FIFOF::*;
import GetPut::*;
import Vector::*;

/**
 * How to use this package:
 *
 * # printTrace, fprintTrace
 *
 * Let's say you have an interface method in your module that is directly
 * connected to a submodule's interface method, but you want to add a print
 * statement to it. If you don't want to go through the trouble of writing a
 * method definition just to print a message and call the submodule, you can
 * use printTrace and/or fprintTrace to attach a message to the Action or
 * ActionValue interface method every time it is called.
 *
 * >  method Action clear = submodule.clear;
 *
 * becomes
 *
 * >  method Action clear = printTrace("clear", submodule.clear);
 *
 * This will print "clear" to stdout every time the clear method is called. To
 * print to a different file, you can use fprintTrace and specify the file.
 *
 * If your method takes in arguments, printTrace will print the values of the
 * arguments when it is callled. For example:
 *
 * >  method Action enq = printTrace("enq", submodule.enq);
 *
 * will print messages like this:
 *
 * >  enq(3)
 * >  enq(8)
 *
 * This only works if there is an appropriate instance of FShow for all the
 * argument types. You can use printTrace on method calls within a rule, but
 * depending on how you write it, you may or may not see the arguments used in
 * the method call. For example, if you have the original method call:
 *
 * >  m.foo(2, 9);
 *
 * Then writing this ........................ will print this
 * >  printTrace("m.foo", m.foo(2, 9))        >  submodule.foo
 * >  printTrace("m.foo", m.foo)(2, 9)        >  submodule.foo(2, 9)
 * >  printTrace("m.foo", m.foo, 2, 9)        >  submodule.foo(2, 9)
 *
 * # printTraceM, fprintTraceM
 *
 * Let's say you have a FIFO in your module, and you want to add print
 * statements to it's interface:
 *
 * >  FIFO#(Bit#(4)) myfifo <- mkFIFO;
 *
 * becomes
 *
 * >  FIFO#(Bit#(4)) myfifo <- printTraceM("myfifo", mkFIFO);
 *
 * Now everytime any of the action interface methods are called, a message is
 * printed to stdout like this:
 *
 * >  myfifo.enq(3) =
 * >  myfifo.enq(0) =
 * >  myfifo.deq = 3
 * >  myfifo.deq = 0
 * >  myfifo.enq(1) =
 * >  myfifo.deq = 1
 *
 * If you want to output that information to a file, you can use fprintTraceM:
 *
 * >  FIFO#(Bit#(4)) myfifo <- fprintTraceM(file, "myfifo", mkFIFO);
 *
 * You can print to stderr by specifying the file as stderr.
 *
 */

// TODO:
// * Figure out how to add an instance of HasFPrintTraceHelper for Action
//   (which is an alias for ActionValue#(void)) without breaking provisos for
//   other functions and instances using FShow#(t) to imply the existence of
//   ActionValue#(t).
// * Make real documentation.

typeclass HasTypeIsVoid#(type t);
    function Bool typeIsVoid(t x);
        return False;
    endfunction
endtypeclass
instance HasTypeIsVoid#(void);
    function Bool typeIsVoid(void x);
        return True;
    endfunction
endinstance

// internal typeclass
typeclass HasFPrintTraceHelper#(type t);
    function t fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, t x);
endtypeclass
// Base case: ActionValue#(t) (This covers Action since Action = ActionValue#(void))
instance HasFPrintTraceHelper#(ActionValue#(t)) provisos (FShow#(t));
    function ActionValue#(t) fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, ActionValue#(t) av);
        return (actionvalue
                t x <- av;
                Fmt printFmt = callName;
                if (args matches tagged Valid .validArgs) begin
                    printFmt = printFmt + $format("(", validArgs, ")");
                end
                // if (t != void)
                void v = ?;
                if (typeOf(x) != typeOf(v)) begin
                    printFmt = printFmt + $format(" = ", fshow(x));
                end
                $fdisplay(file, printFmt);
                $fflush(file);
                return x;
            endactionvalue);
    endfunction
endinstance
// Adding an argument
instance HasFPrintTraceHelper#(function outT f(inT x)) provisos (HasFPrintTraceHelper#(outT), FShow#(inT));
    function (function outT f(inT x)) fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, function outT func(inT x));
        function outT retFunc(inT x);
            Fmt newArgs = args matches tagged Valid .validArgs ? validArgs + $format(", ") + fshow(x) : fshow(x);
            return fprintTraceHelper(file, callName, tagged Valid newArgs, func(x));
        endfunction
        return retFunc;
    endfunction
endinstance
// Some interfaces
instance HasFPrintTraceHelper#(Reg#(t)) provisos (FShow#(t));
    function Reg#(t) fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, Reg#(t) ifc);
        // if there were arguments, add it to the callName
        Fmt newCallName = args matches tagged Valid .validArgs ? $format(callName, "(", validArgs, ")") : callName;
        Maybe#(Fmt) newArgs = tagged Invalid;
        return (interface Reg;
                    method Action _write(t x) = fprintTraceHelper(file, $format(newCallName, "._write"), newArgs, ifc._write, x);
                    method t _read = ifc._read;
                endinterface);
    endfunction
endinstance
instance HasFPrintTraceHelper#(Get#(t)) provisos (FShow#(t));
    function Get#(t) fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, Get#(t) ifc);
        // if there were arguments, add it to the callName
        Fmt newCallName = args matches tagged Valid .validArgs ? $format(callName, "(", validArgs, ")") : callName;
        Maybe#(Fmt) newArgs = tagged Invalid;
        return toGet(fprintTraceHelper(file, $format(newCallName, ".get"), newArgs, ifc.get));
    endfunction
endinstance
instance HasFPrintTraceHelper#(Put#(t)) provisos (FShow#(t));
    function Put#(t) fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, Put#(t) ifc);
        // if there were arguments, add it to the callName
        Fmt newCallName = args matches tagged Valid .validArgs ? $format(callName, "(", validArgs, ")") : callName;
        Maybe#(Fmt) newArgs = tagged Invalid;
        return toPut(fprintTraceHelper(file, $format(newCallName, ".put"), newArgs, ifc.put));
    endfunction
endinstance
instance HasFPrintTraceHelper#(Client#(t1,t2)) provisos (FShow#(t1), FShow#(t2));
    function Client#(t1,t2) fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, Client#(t1,t2) ifc);
        // if there were arguments, add it to the callName
        Fmt newCallName = args matches tagged Valid .validArgs ? $format(callName, "(", validArgs, ")") : callName;
        Maybe#(Fmt) newArgs = tagged Invalid;
        return toGPClient(fprintTraceHelper(file, $format(newCallName, ".request"), newArgs, ifc.request),
                          fprintTraceHelper(file, $format(newCallName, ".response"), newArgs, ifc.response));
    endfunction
endinstance
instance HasFPrintTraceHelper#(Server#(t1,t2)) provisos (FShow#(t1), FShow#(t2));
    function Server#(t1,t2) fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, Server#(t1,t2) ifc);
        // if there were arguments, add it to the callName
        Fmt newCallName = args matches tagged Valid .validArgs ? $format(callName, "(", validArgs, ")") : callName;
        Maybe#(Fmt) newArgs = tagged Invalid;
        return toGPServer(fprintTraceHelper(file, $format(newCallName, ".request"), newArgs, ifc.request),
                          fprintTraceHelper(file, $format(newCallName, ".response"), newArgs, ifc.response));
    endfunction
endinstance
instance HasFPrintTraceHelper#(FIFO#(t)) provisos (FShow#(t));
    function FIFO#(t) fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, FIFO#(t) ifc);
        // if there were arguments, add it to the callName
        Fmt newCallName = args matches tagged Valid .validArgs ? $format(callName, "(", validArgs, ")") : callName;
        Maybe#(Fmt) newArgs = tagged Invalid;
        return (interface FIFO;
                    method Action enq(t x); fprintTraceHelper(file, $format(newCallName, ".enq"), newArgs, ifc.enq, x); endmethod
                    // when printing, make deq look like an action value so you can see the value of first
                    method Action deq = fprintTraceHelper(file, $format(newCallName, ".deq = ", fshow(ifc.first)), newArgs, ifc.deq);
                    method t first = ifc.first;
                    method Action clear = fprintTraceHelper(file, $format(newCallName, ".clear"), newArgs, ifc.clear);
                endinterface);
    endfunction
endinstance
instance HasFPrintTraceHelper#(FIFOF#(t)) provisos (FShow#(t));
    function FIFOF#(t) fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, FIFOF#(t) ifc);
        // if there were arguments, add it to the callName
        Fmt newCallName = args matches tagged Valid .validArgs ? $format(callName, "(", validArgs, ")") : callName;
        Maybe#(Fmt) newArgs = tagged Invalid;
        return (interface FIFOF;
                    method Action enq(t x) = fprintTraceHelper(file, $format(newCallName, ".enq"), newArgs, ifc.enq, x);
                    // when printing, make deq look like an action value so you can see the value of first
                    method Action deq = fprintTraceHelper(file, $format(newCallName, ".deq = ", fshow(ifc.first)), newArgs, ifc.deq);
                    method t first = ifc.first;
                    method Bool notFull = ifc.notFull;
                    method Bool notEmpty = ifc.notEmpty;
                    method Action clear = fprintTraceHelper(file, $format(newCallName, ".clear"), newArgs, ifc.clear);
                endinterface);
    endfunction
endinstance
instance HasFPrintTraceHelper#(Vector#(n,t)) provisos (HasFPrintTraceHelper#(t));
    function Vector#(n,t) fprintTraceHelper(File file, Fmt callName, Maybe#(Fmt) args, Vector#(n,t) ifc);
        // if there were arguments, add it to the callName
        Fmt newCallName = args matches tagged Valid .validArgs ? $format(callName, "(", validArgs, ")") : callName;
        Maybe#(Fmt) newArgs = tagged Invalid;

        function t genFunc(Integer i);
            return fprintTraceHelper(file, $format(callName, "[%d]", i), tagged Invalid, ifc[i]);
        endfunction
        return genWith(genFunc);
    endfunction
endinstance

// external functions
function t fprintTrace(File file, String msg, t x)
        provisos (HasFPrintTraceHelper#(t));
    return fprintTraceHelper(file, $format(msg), tagged Invalid, x);
endfunction

function t printTrace(String msg, t x)
        provisos (HasFPrintTraceHelper#(t));
    return fprintTraceHelper(stdout, $format(msg), tagged Invalid, x);
endfunction

module [m] fprintTraceM#(File file, String msg, m#(t) mkM)(t)
        provisos (IsModule#(m, a__), HasFPrintTraceHelper#(t));
    (* hide *)
    t _m <- mkM();
    return fprintTraceHelper(file, $format(msg), tagged Invalid, _m);
endmodule

module [m] printTraceM#(String msg, m#(t) mkM)(t)
        provisos (IsModule#(m, a__), HasFPrintTraceHelper#(t));
    (* hide *)
    t _m <- mkM;
    return fprintTraceHelper(stdout, $format(msg), tagged Invalid, _m);
endmodule

endpackage

error: pathspec 'hw/bsv/PrintTrace.bsv' did not match any file(s) known to git


abstract link receiver, so I can use it for both data and flow control

// Copyright (c) 2014 Quanta Research Cambridge, Inc.
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

import FIFO::*;

/* This is a serial to parallel converter for messages of type a
 * The data register is assumed to always be available, so an arriving
 * message must be removed ASAP or be overwritten
 */
interface LinkIn#(type a);
   method Action frame(bit f);
   method Action data(bit d);
   interface Reg#(Bool) dataready;
   interface ReadOnly#(a) ror;
endinterface

module mkLinkIn(LinkIn#(a))
       provisos(Bits#(a,asize)),
	        Log#(asize, k);

   // registers for receiving data messages
   Reg#(bit) framebit <- mkReg(0);
   Reg#(bit) databit <- mkReg(0);
   Reg#(Bit#(6)) incount <= mkReg(0);
   Reg#(a) shifter <- mkReg(0);
   Reg#(a) data <- mkReg(0);
   FIFOF#(?) <- mkSizedFIFOF(1);

   rule handleDataFrame;
      if (datainframebit == 0)
	 begin
            dataincount <= 0;
	 end
      else
	 dataincount <= dataincount + 1;
   endrule

   rule handleDataInShift (datainframebit == 1);
      Bit#(SizeOf(DataMessage)) tmp = datainshifter;
      tmp = tmp >> 1;
      tmp[SizeOf(DataMessage)-1] = datainbit;
      datainshifter <= tmp;
      if (dataincount == (SizeOf(DataMessage) - 1))
         action
	    new <= tmp;
	    dataready <= True;
	 end;
   endrule

   interface LinkIn;

      method Action frame(bit i );
	 frameinbit <= i ;
      endmethod

      method Action data( bit i );
	 datainbit <= i;
      endmethod

      interface ReadOnly#(a) ror = regToReadOnly(r);

      interface Reg#(Bool) ready = dataready;

   endinterface

endmodule

error: pathspec 'examples/noc/LinkIn.bsv' did not match any file(s) known to git


in order reservation station; untested

in order reservation station; untested

// Copyright (c) 2019 Massachusetts Institute of Technology
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

import Vector::*;
import ConfigReg::*;
import Assert::*;
import Ehr::*;
import Types::*;
import ProcTypes::*;
import HasSpecBits::*;

// Reservation station used in in-order core to hold instructions after
// renaming. This is simply a FIFO, and instructions are ordered in program
// order. Outside rules only inspect the head of the FIFO, i.e., there is no
// need to receive "wake up" from outside. Killing is also simplified: we can
// just move the enqP.

typedef struct {
    dataT data; // payload for this inst
    PhyRegs regs;
    InstTag tag;
    // speculation
    SpecBits spec_bits;
    Maybe#(SpecTag) spec_tag;
} ToInorderRS#(type dataT) deriving(Bits, Eq, FShow);

interface InorderRS#(numeric type size, type dataT);
    method Action enq(ToInorderRS#(dataT) x);
    method Bool canEnq;

    method ToInorderRS#(dataT) first;
    method Action deq;

    // For count-based scheduling when there are multiple reservation stations
    // for the same inst type. This method only takes effect when module
    // parameter countValid is true.
    method Bit#(TLog#(TAdd#(size, 1))) approximateCount;

    // performance: count full cycles
    method Bool isFull_ehrPort0;

    interface SpeculationUpdate specUpdate;
endinterface

// schedule:
// deq < enq < correctSpec
// (deq, enq) C wrongSpec

module mkInorderRS#(Bool lazyEnq, Bool countValid)(
    InorderRS#(size, dataT)
) provisos (
    Alias#(idxT, Bit#(TLog#(size))),
    Alias#(virIdxT, Bit#(TLog#(TMul#(2, size)))), // virtual index
    Alias#(countT, Bit#(TLog#(TAdd#(size, 1)))),
    Log#(TAdd#(1, size), TLog#(TAdd#(size, 1))),
    Bits#(dataT, a__),
    Add#(1, b__, size)
);
    Vector#(size, Ehr#(2, Bool))         valid    <- replicateM(mkEhr(False));
    Vector#(size, Reg#(dataT))           data     <- replicateM(mkRegU);
    Vector#(size, Reg#(PhyRegs))         regs     <- replicateM(mkRegU);
    Vector#(size, Reg#(InstTag))         instTag  <- replicateM(mkRegU);
    Vector#(size, Reg#(Maybe#(SpecTag))) specTag  <- replicateM(mkRegU);
    Vector#(size, Ehr#(2, SpecBits))     specBits <- replicateM(mkEhr(?));

    let valid_deq       = getVEhrPort(valid, 0);
    let valid_wrongSpec = getVEhrPort(valid, 0); // write
    let valid_enq       = getVEhrPort(valid, 1); // write

    let sb_deq         = getVEhrPort(specBits, 0);
    let sb_wrongSpec   = getVEhrPort(specBits, 0);
    let sb_enq         = getVEhrPort(specBits, 0); // write
    let sb_correctSpec = getVEhrPort(specBits, 1); // write

    // create conflicts
    RWire#(void) wrongSpec_enq_conflict <- mkRWire;
    RWire#(void) wrongSpec_deq_conflict <- mkRWire;

    Reg#(idxT) enqP <- mkReg(0);
    Reg#(idxT) deqP <- mkReg(0);

    function idxT getNextPtr(idxT i);
        return i == fromInteger(valueOf(size) - 1) ? 0 : i + 1;
    endfunction

    // We use virtual index to determine which is the oldest entry being
    // killed.  Since enqP is not changed during all the cycle, we map index to
    // virtual index using enqP as pivot.
    // The mapping is as follow:
    // - valid entry i --> i < enqP ? i + QSize : i
    // XXX This mapping is only for comparing valid entries (e.g., it may not
    // work properly for enqP), so we must check entry valid before using
    // virtual index.
    function virIdxT getVirIdx(idxT i);
        return i < enqP ? zeroExtend(i) + fromInteger(valueof(size))
                        : zeroExtend(i);
    endfunction
    // Virtual index
    Vector#(size, virIdxT) virIdxes = map(getVirIdx. genWith(fromInteger));

    // find the oldest entry that satisfies a constraint (i.e. smallest virtual
    // index)
    function Maybe#(idxT) findOldest(Vector#(size, Bool) pred);
        function idxT getOlder(idxT a, idxT b);
            if(!pred[a]) begin
                return b;
            end
            else if(!pred[b]) begin
                return a;
            end
            else begin
                return virIdxes[a] < virIdxes[b] ? a : b;
            end
        endfunction
        Vector#(size, idxT) idxVec = genWith(fromInteger);
        idxT i  = fold(getOlder, idxVec);
        return pred[i] ? Valid (i) : Invalid;
    endfunction

    // approximate count of valid entries
    Reg#(countT) validEntryCount <- mkConfigReg(0);

    if(countValid) begin
        (* fire_when_enabled, no_implicit_conditions *)
        rule countValidEntries;
            validEntryCount <= pack(countElem(True, readVEhr(0, valid)));
        endrule
    end

    // can enq signal for enq port
    Bool can_enq;
    if(lazyEnq) begin
        Wire#(Bool) can_enq_wire <- mkBypassWire;
        (* fire_when_enabled, no_implicit_conditions *)
        rule setCanEnq;
            can_enq_wire <= !valid[enqP][0];
        endrule
        can_enq = can_enq_wire;
    end
    else begin
        can_enq = !valid_enq[enqP];
    end

    // can deq sigal for deq port
    Bool can_deq = valid_deq[deqP];

`ifdef BSIM
    // Sanity check in simulation. All valid entry are consective within deqP
    // and enqP, outsiders are invalid entries
    (* fire_when_enabled, no_implicit_conditions *)
    rule checkValid;
        if(all(\== (False),  readVEhr(0, valid))) begin
            doAssert(enqP == deqP, "empty queue have enqP = deqP");
        end
        else begin
            // not empty queue, check valid entries with [deqP, enqP)
            function Bool in_range(idxT i);
                if(deqP < enqP) begin
                    return deqP <= i && i < enqP;
                end
                else begin
                    return deqP <= i || i < enqP;
                end
            endfunction
            for(Integer i = 0; i < valueof(size); i = i+1) begin
                doAssert(in_range(fromInteger(i)) == valid[i][0],
                         "valid entries must be within [deqP, enqP)");
            end
        end
    endrule
`endif

    method Action enq(ToInorderRS#(dataT) x) if(can_enq);
        doAssert(!valid_enq[enqP], "enqP entry must be invalid");
        // set contents
        data[enqP] <= x.data;
        regs[enqP] <= x.regs;
        instTag[enqP] <= x.tag;
        specTag[enqP] <= x.spec_tag;
        sb_enq[enqP] <= x.spec_bits;
        // set valid, move ptr
        valid_enq[enqP] <= True;
        enqP <= getNextPtr(enqP);
        // make conflict with wrong spec
        wrongSpec_enq_conflict.wset(?);
    endmethod

    method Bool canEnq = can_enq;

    method ToInorderRS#(dataT) first if(can_deq);
        return ToInorderRS {
            data: data[deqP],
            regs: regs[deqP],
            tag: instTag[deqP],
            spec_bits: sb_deq[deqP],
            spec_tag: specTag[deqP]
        };
    endmethod

    method Action deq if(can_deq);
        valid_deq[deqP] <= False;
        deqP <= getNextPtr(deqP);
        // make conflict with wrong spec
        wrongSpec_deq_conflict.wset(?);
    endmethod

    method countT approximateCount;
        return validEntryCount;
    endmethod

    method Bool isFull_ehrPort0;
        return readVEhr(0, valid) == replicate(True);
    endmethod

    interface SpeculationUpdate specUpdate;
        method Action correctSpeculation(SpecBits mask);
            function Action correctSpec(idxT i);
            action
                sb_correctSpec[i] <= sb_correctSpec[i] & mask;
            endaction
            endfunction
            Vector#(size, idxT) idxVec = genWith(fromInteger);
            joinActions(map(correctSpec, idxVec));
        endmethod

        method Action incorrectSpeculation(Bool killAll, SpecTag killSpecTag);
            // clear wrong path entries
            Vector#(size, idxT) idxVec = genWith(fromInteger);
            function Bool isNeedKill(idxT i);
                return killAll || sb_wrongSpec[i][killSpecTag] == 1;
            endfunction
            Vector#(size, Bool) needKill = map(isNeedKill, idxVec);
            function Action kill(idxT i);
            action
                if(needKill[i]) begin
                    valid_wrongSpec[i] <= False;
                end
            endaction
            endfunction
            joinActions(map(kill, idxVec));

            // change enqP: make valid entries always consecutive: new enqP is
            // the oldest **VALID** entry that gets killed. If such entry does
            // not exists, then enqP remains the same.
            function Bool isValidKilled(idxT i);
                return valid_wrongSpec[i] && needKill[i];
            endfunction
            Vector#(size, Bool) killedValid = map(isValidKilled, idxVec);
            idxT new_enqP = enqP;
            if(findOldest(killedValid) matches tagged Valid .idx) begin
                new_enqP = idx;
            end
            ld_enqP <= new_enqP;

            // conflict with enq, deq
            wrongSpec_enq_conflict.wset(?);
            wrongSpec_deq_conflict.wset(?);
        endmethod
    endinterface
endmodule

error: pathspec 'procs/lib/InorderRS.bsv' did not match any file(s) known to git


removed MemUtils by accident

removed MemUtils by accident

// Copyright (c) 2013 Quanta Research Cambridge, Inc.

// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

import BRAM::*;
import FIFO::*;
import Vector::*;
import Gearbox::*;
import FIFOF::*;
import SpecialFIFOs::*;

import BRAMFIFOFLevel::*;
import GetPut::*;
import Dma::*;

interface MemReader#(numeric type dataWidth);
   interface ObjectReadServer #(dataWidth) readServer;
   interface ObjectReadClient#(dataWidth) readClient;
endinterface

module mkMemReader(MemReader#(dataWidth))
   provisos(Div#(dataWidth,8,dataWidthBytes),
	    Mul#(dataWidthBytes,8,dataWidth),
	    Log#(dataWidthBytes,beatShift));

   FIFOF#(ObjectData#(dataWidth))  readBuffer <- mkFIFOF;
   FIFOF#(ObjectRequest)       reqOutstanding <- mkFIFOF;

   interface ObjectReadServer readServer;
      interface Put readReq = toPut(reqOutstanding);
      interface Get readData = toGet(readBuffer);
   endinterface
   interface ObjectReadClient readClient;
      interface Get readReq = toGet(reqOutstanding);
      interface Put readData = toPut(readBuffer);
   endinterface
endmodule

interface MemWriter#(numeric type dataWidth);
   interface ObjectWriteServer#(dataWidth) writeServer;
   interface ObjectWriteClient#(dataWidth) writeClient;
endinterface

module mkMemWriter(MemWriter#(dataWidth))
   provisos(Div#(dataWidth,8,dataWidthBytes),
	    Mul#(dataWidthBytes,8,dataWidth),
	    Log#(dataWidthBytes,beatShift));

   FIFOF#(ObjectData#(dataWidth)) writeBuffer <- mkFIFOF;
   FIFOF#(ObjectRequest)        reqOutstanding <- mkFIFOF;
   FIFOF#(Bit#(6))                        doneTags <- mkFIFOF();

   interface ObjectWriteServer writeServer;
      interface Put writeReq = toPut(reqOutstanding);
      interface Put writeData = toPut(writeBuffer);
      interface Get writeDone = toGet(doneTags);
   endinterface
   interface ObjectWriteClient writeClient;
      interface Get writeReq = toGet(reqOutstanding);
      interface Get writeData = toGet(writeBuffer);
      interface Put writeDone = toPut(doneTags);
   endinterface

endmodule

error: pathspec 'bsv/MemUtils.bsv' did not match any file(s) known to git


Added Scoreboard

Added Scoreboard

import SearchFIFO::*;
import RVTypes::*;

interface Scoreboard#(numeric type size);
    method Action insert(Maybe#(FullRegIndex) fullRegIndex);
    method Action remove;
    method Bool search1(Maybe#(FullRegIndex) fullRegIndex);
    method Bool search2(Maybe#(FullRegIndex) fullRegIndex);
    method Bool search3(Maybe#(FullRegIndex) fullRegIndex);
    method Bool notEmpty;
    method Action clear;
endinterface

module mkScoreboard(Scoreboard#(size));
    function Bool isFound(Maybe#(FullRegIndex) x, Maybe#(FullRegIndex) y);
        return isValid(x) && isValid(y) && x == y;
    endfunction

    SearchFIFO#(size, Maybe#(FullRegIndex), Maybe#(FullRegIndex)) f <- mkSearchFIFO(isFound);

    method insert = f.enq;
    method remove = f.deq;
    method search1 = f.search;
    method search2 = f.search;
    method search3 = f.search;
    method notEmpty = f.notEmpty;
    method clear = f.clear;
endmodule

error: pathspec 'procs/lib/Scoreboard.bsv' did not match any file(s) known to git


Algo1Nandsim.bsv

import GetPut::*;
import Connectable::*;
import Vector::*;
import BuildVector::*;

import ConnectalConfig::*;
import ConnectalMemory::*;
import MemTypes::*;
import MemServer::*;
import MMU::*;

import NandSim::*;
import Strstr::*;

interface Algo1NandSim;
   interface NandCfgRequest   nandCfgRequest;
   interface MMURequest       nandMMURequest;
   interface MemServerRequest nandMemServerRequest;
   interface StrstrRequest    strstrRequest;
   interface Vector#(2, MemReadClient#(DataBusWidth)) dmaReadClients;
   interface Vector#(1, MemWriteClient#(DataBusWidth)) dmaWriteClients;
endinterface

module mkAlgo1NandSim#(NandCfgIndication nandCfgIndication, MMUIndication nandMMUIndication, MemServerIndication nandSimMemServerIndication, StrstrIndication strstrIndication)(Algo1NandSim);

   Strstr#(64,64) strstr <- mkStrstr(strstrIndication);

   NandSim nandSim <- mkNandSim(nandCfgIndication);
   MMU#(PhysAddrWidth) nandMMU <- mkMMU(0, False, nandMMUIndication);
   MemServer#(PhysAddrWidth,64,1) nandSimMemServer <- mkMemServer(strstr.haystack_read_client, nil, vec(nandMMU), nandSimMemServerIndication);
   let nandSimMemCnx <- mkConnection(nandSimMemServer.masters[0], nandSim.memSlave);
   // rule rl_readReq;
   //    let req <- nandSimMemServer.masters[0].read_client.readReq.get();
   //    $display("rl_readReq addr=%h", req.addr);
   //    nandSim.memSlave.read_server.readReq.put(req);
   // endrule

   // let readDataCnx  <- mkConnection(nandSimMemServer.masters[0].read_client.readData, nandSim.memSlave.read_server.readData);
   // let writeReqCnx  <- mkConnection(nandSimMemServer.masters[0].write_client.writeReq, nandSim.memSlave.write_server.writeReq);
   // let writeDataCnx <- mkConnection(nandSimMemServer.masters[0].write_client.writeData, nandSim.memSlave.write_server.writeData);
   // let writeDoneCnx <- mkConnection(nandSimMemServer.masters[0].write_client.writeDone, nandSim.memSlave.write_server.writeDone);

   interface dmaReadClients = append(nandSim.readClient, strstr.config_read_client);
   interface dmaWriteClients = nandSim.writeClient;

   interface nandCfgRequest          = nandSim.request;
   interface nandMMURequest          = nandMMU.request;
   interface strstrRequest           = strstr.request;
   interface nandMemServerRequest    = nandSimMemServer.request;
endmodule

error: pathspec 'examples/algo1_nandsim/Algo1NandSim.bsv' did not match any file(s) known to git


Added StmtFSMExtra.bsv to avoid a name conflict with the open-sourced compiler

// Copyright (c) 2017 Massachusetts Institute of Technology

// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

/// This is a copy of StmtFSMUtil to avoid a name conflict with the
/// StmtFSMUtil package that is part of the open-sourced Bluespec
/// compiler.
package StmtFSMExtra;

import ConfigReg::*;
import StmtFSM::*;

import Ehr::*;

interface FlexFSM;
    method Action start;
    method Bool running_schedBeforeStart;
    method Bool running_schedAfterStart;
endinterface

module mkFlexFSM#(Stmt seq_stmt)(FlexFSM);
    Reg#(Bool) running_config_reg <- mkConfigReg(False);
    Ehr#(2, Bool) running <- mkEhr(False);
    FSM _fsm <- mkFSMWithPred(seq seq_stmt; action running[0] <= False; running_config_reg <= False; endaction endseq, running_config_reg);

    method Action start if (!running[0]);
        running[0] <= True;
        running_config_reg <= True;
        _fsm.start;
    endmethod
    method Bool running_schedBeforeStart;
        return running[0] || running_config_reg;
    endmethod
    method Bool running_schedAfterStart;
        return running[1] || running_config_reg;
    endmethod
endmodule

module mkSafeFSM#(Stmt seq_stmt)(FSM);
    Reg#(Bool) fsmRunning <- mkReg(False);
    FSM _fsm <- mkFSMWithPred(seq seq_stmt; fsmRunning <= False; endseq, fsmRunning);

    method Action start if (!fsmRunning);
        fsmRunning <= True;
        _fsm.start;
    endmethod

    method Action waitTillDone;
        _fsm.waitTillDone;
    endmethod

    method Bool done;
        return !fsmRunning;
    endmethod

    method Action abort if (False);
        noAction;
    endmethod
endmodule

module mkBypassFSM#(Stmt seq_stmt)(FSM);
    Ehr#(2, Bool) fsmRunning <- mkEhr(False);
    FSM _fsm <- mkFSMWithPred(seq seq_stmt; fsmRunning[0] <= False; endseq, fsmRunning[0]);

    method Action start if (!fsmRunning[0]);
        fsmRunning[0] <= True;
        _fsm.start;
    endmethod

    method Action waitTillDone;
        _fsm.waitTillDone;
    endmethod

    method Bool done;
        return !fsmRunning[1];
    endmethod

    method Action abort if (False);
        noAction;
    endmethod
endmodule

endpackage

error: pathspec 'src/bsv/StmtFSMExtra.bsv' did not match any file(s) known to git


actual pktgen.bsv

actual pktgen.bsv

// Copyright (c) 2014 Cornell University.

// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

import FIFO::*;
import FIFOF::*;
import DefaultValue::*;
import Vector::*;
import BuildVector::*;
import GetPut::*;
import ClientServer::*;
import Connectable::*;
import Clocks::*;
import Gearbox::*;
import Pipe::*;
import Ethernet::*;
import PacketBuffer::*;

typedef 1 BaseIdle;

interface PktGen;
    interface PktWriteServer writeServer;
    interface PktWriteClient writeClient;
    method Action start(Bit#(32) iter, Bit#(32) ipg);
    method Action stop();
    method Action clear();
endinterface

module mkPktGen(PktGen)
   provisos (Div#(`DataBusWidth, 8, bytesPerBeat)
            ,Log#(bytesPerBeat, beatShift));

    Reg#(Bit#(32)) traceLen <- mkReg(0);
    Reg#(Bit#(32)) count <- mkReg(0);
    Reg#(Bit#(32)) iteration <- mkReg(0);
    Reg#(Bit#(32)) total_ipg <- mkReg(0);
    Reg#(Bool) started <- mkReg(False);
    Reg#(Bool) halt <- mkReg(False);
    Reg#(Bool) idle <- mkReg(False);
    Reg#(Bit#(32)) curr_ipg <- mkReg(0);

    FIFO#(EtherData) outgoing_fifo <- mkFIFO();
    PacketBuffer buff <- mkPacketBuffer();

    rule fetch_packet if (started && !halt && !idle);
        let pktLen <- buff.readServer.readLen.get;
        buff.readServer.readReq.put(EtherReq{len:pktLen});
        $display("fetch packet");
    endrule

    rule enqueue_packet if (started && !halt && !idle);
        let data <- buff.readServer.readData.get;
        buff.writeServer.writeData.put(data);
        outgoing_fifo.enq(data);
        if (data.eop) begin
            count <= count + 1;
            idle <= True;
            curr_ipg <= 0;
            $display("eop %h %h %h %h %h", halt, idle, started, curr_ipg, total_ipg);
        end
    endrule

    rule terminate if (started && (count > iteration));
        halt <= True;
    endrule

    rule gen_ipg if ((curr_ipg < total_ipg + fromInteger(valueOf(BaseIdle))) && idle);
        curr_ipg <= curr_ipg + fromInteger(valueOf(bytesPerBeat));
        $display("ipg = %d", curr_ipg);
    endrule

    rule next_packet if ((curr_ipg >= total_ipg + fromInteger(valueOf(BaseIdle))));
        EtherData v = defaultValue;
        idle <= False;
        curr_ipg <= 0;
    endrule

    interface PktWriteServer writeServer;
        interface Put writeData;
            method Action put (EtherData d);
                buff.writeServer.writeData.put(d);
                if (d.eop) begin
                    traceLen <= traceLen + 1;
                end
            endmethod
        endinterface
    endinterface
    interface PktWriteClient writeClient;
        interface Get writeData = toGet(outgoing_fifo);
    endinterface
    method Action clear();
    endmethod
    method Action start(Bit#(32) iter, Bit#(32) ipg) if (!started);
        started <= True;
        halt <= False;
        total_ipg <= ipg;
        iteration <= iter;
        $display("start %h %h", iter, ipg);
    endmethod
    method Action stop() if (started);
        started <= False;
    endmethod
endmodule

error: pathspec 'hw/bsv/PktGen.bsv' did not match any file(s) known to git


fix endmodule

fix endmodule

// Copyright (c) 2013 Quanta Research Cambridge, Inc.

// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

import FIFO::*;
import GetPut::*;
import ClientServer::*;

module mkEchoServer#() ( Server#(Bit#(64), Bit#(64)));
   FIFO#(Bit#(64)) f_echo  <- mkSizedFIFOF(16);    // to buffer incoming requests

   interface Put request = toPut(f_echo);
   interface Get response = toGet (f_echo);

endmodule: mkEchoServer

error: pathspec 'examples/ring/EchoServer.bsv' did not match any file(s) known to git


initial version of SATD[8x8]

initial version of SATD[8x8]

// Copyright (c) 2016-2017 Min Chen
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//

import ConfigReg::*;
import Vector::*;
import GetPut::*;
import FIFOF::*;
import SpecialFIFOs::*;
import BUtils::*;

interface ISatd8;
   interface Put#(Vector#(8, Bit#(9))) inp;
   interface Get#(Vector#(1, Bit#(16))) oup;
endinterface

function Vector#(8, Bit#(na)) satd_1d(Vector#(8, Bit#(n)) x)
   provisos(
      Add#(n, 3, na)
   );
   Vector#(8, Bit#(na)) m0;
   Vector#(8, Bit#(na)) m1;
   Vector#(8, Bit#(na)) m2;

   m0[0] = sExtend(x[0]) + sExtend(x[4]);
   m0[1] = sExtend(x[1]) + sExtend(x[5]);
   m0[2] = sExtend(x[2]) + sExtend(x[6]);
   m0[3] = sExtend(x[3]) + sExtend(x[7]);
   m0[4] = sExtend(x[0]) - sExtend(x[4]);
   m0[5] = sExtend(x[1]) - sExtend(x[5]);
   m0[6] = sExtend(x[2]) - sExtend(x[6]);
   m0[7] = sExtend(x[3]) - sExtend(x[7]);

   m1[0] = m0[0] + m0[2];
   m1[1] = m0[1] + m0[3];
   m1[2] = m0[0] - m0[2];
   m1[3] = m0[1] - m0[3];
   m1[4] = m0[4] + m0[6];
   m1[5] = m0[5] + m0[7];
   m1[6] = m0[4] - m0[6];
   m1[7] = m0[5] - m0[7];

   m2[0] = m0[0] + m0[1];
   m2[1] = m0[0] - m0[1];
   m2[2] = m0[2] + m0[3];
   m2[3] = m0[2] - m0[3];
   m2[4] = m0[4] + m0[5];
   m2[5] = m0[4] - m0[5];
   m2[6] = m0[6] + m0[7];
   m2[7] = m0[6] - m0[7];

   return m2;
endfunction

(* synthesize *)
module mkSatd8(ISatd8);
   FIFOF#(Vector#(8, Bit#(9)))               fifo_inp     <- mkPipelineFIFOF;
   FIFOF#(Vector#(1, Bit#(16)))              fifo_out    <- mkPipelineFIFOF;

   RWire#(Vector#(8, Bit#(12)))              rw_trans    <- mkRWire;
   RWire#(Bool)                              rw_oflag    <- mkRWire;

   Reg#(Bit#(16))                            flags       <- mkConfigReg(0);
   Reg#(Bool)                                dir         <- mkConfigReg(True);
   Vector#(8, Reg#(Vector#(8, Bit#(12))))    matrix      <- replicateM(mkConfigRegU);

   rule shift_matrix(isValid(rw_trans.wget) || flags[15:8] != 0);
      let x = fromMaybe(?, rw_trans.wget);
      let y = isValid(rw_trans.wget) ? 1 : 0;

      if (dir) begin
         // Row shift
         for(Integer i = 0; i < 8 - 1; i = i + 1) begin
            matrix[i] <= matrix[i + 1];
         end
         matrix[8 - 1] <= x;
      end
      else begin
         // Column shift
         for(Integer i = 0; i < 8; i = i + 1) begin
            matrix[i] <= shiftInAtN(matrix[i], x[i]);
         end
      end

      let next_flags = flags * 2 + y;
      flags <= next_flags;
      if (next_flags == '1)
         dir <= !dir;
   endrule

   rule do_2d(flags[15:8] != 0);
      Vector#(8, Bit#(12)) tmp = ?;

      if (dir) begin
         tmp = matrix[0];
      end
      else begin
         for(Integer i = 0; i < 8; i = i + 1) begin
            tmp[i] = matrix[i][0];
         end
      end
      let x = satd_1d(tmp);
      Vector#(1, Bit#(16)) sum = unpack(0);

      for(Integer i = 0; i < 8; i = i + 1) begin
         Int#(15) v = unpack(x[i]);
         sum[0] = sum[0] + zExtend(pack(abs(v)));
      end

      fifo_out.enq(sum);
   endrule

   rule do_1d(fifo_inp.notEmpty());
      let x = fifo_inp.first;
      fifo_inp.deq;

      let y = satd_1d(x);

      rw_trans.wset(y);
   endrule

   interface Put inp = toPut(fifo_inp);
   interface Get oup = toGet(fifo_out);
endmodule

error: pathspec 'src/mkSatd.bsv' did not match any file(s) known to git


moving some experimental code

moving some experimental code

// Copyright (c) 2013 Quanta Research Cambridge, Inc.

// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

// BSV Libraries
import FIFO::*;
import Vector::*;
import GetPut::*;
import ClientServer::*;
import Assert::*;

// XBSV Libraries
import Dma::*;
import PortalMemory::*;
import SGList::*;
import MemServerInternal::*;

`ifdef BSIM
import "BDPI" function ActionValue#(Bit#(32)) pareff(Bit#(32) handle, Bit#(32) size);
`endif

interface MemServer#(numeric type addrWidth, numeric type dataWidth);
   interface DmaConfig request;
   interface MemMaster#(addrWidth, dataWidth) master;
endinterface

module mkMemServer#(DmaIndication dmaIndication,
		    Vector#(numReadClients, ObjectReadClient#(dataWidth)) readClients,
		    Vector#(numWriteClients, ObjectWriteClient#(dataWidth)) writeClients)
   (MemServer#(addrWidth, dataWidth))
   provisos(Add#(1,a__,dataWidth),
	    Add#(b__, TSub#(addrWidth, 12), 32),
	    Add#(c__, 12, addrWidth),
	    Add#(d__, addrWidth, 64),
	    Add#(e__, TSub#(addrWidth, 12), ObjectOffsetSize),
	    Add#(f__, c__, ObjectOffsetSize),
	    Add#(g__, addrWidth, 40),
	    Mul#(TDiv#(dataWidth, 8), 8, dataWidth),
	    Add#(1, numReadClients, augNumReadClients),
	    Add#(1, numWriteClients, augNumWriteClients),
	    Add#(h__, TLog#(augNumReadClients), 6),
	    Add#(i__, TLog#(augNumWriteClients), 6));

   TagGen#(augNumWriteClients,augNumWriteClients) writeTagGen <- mkTagGenIO;
   TagGen#(augNumReadClients,augNumReadClients) readTagGen <- mkTagGenIO;
   let rv <- mkMemServerRW(dmaIndication, readTagGen, writeTagGen,
			   append(readClients,cons(null_object_read_client,nil)),
			   append(writeClients,cons(null_object_write_client,nil)));
   return rv;

endmodule

module mkMemServerOO#(DmaIndication dmaIndication,
		      Vector#(numReadClients, ObjectReadClient#(dataWidth)) readClients,
		      Vector#(numWriteClients, ObjectWriteClient#(dataWidth)) writeClients)
   (MemServer#(addrWidth, dataWidth))
   provisos(Add#(1,a__,dataWidth),
	    Add#(b__, TSub#(addrWidth, 12), 32),
	    Add#(c__, 12, addrWidth),
	    Add#(d__, addrWidth, 64),
	    Add#(e__, TSub#(addrWidth, 12), ObjectOffsetSize),
	    Add#(f__, c__, ObjectOffsetSize),
	    Add#(g__, addrWidth, 40),
	    Mul#(TDiv#(dataWidth, 8), 8, dataWidth),
	    Add#(1, numReadClients, augNumReadClients),
	    Add#(1, numWriteClients, augNumWriteClients));

   TagGen#(augNumWriteClients,32) writeTagGen <- mkTagGenOO;
   TagGen#(augNumReadClients,32) readTagGen <- mkTagGenOO;
   let rv <- mkMemServerRW(dmaIndication, readTagGen, writeTagGen,
			   append(readClients,cons(null_object_read_client,nil)),
			   append(writeClients,cons(null_object_write_client,nil)));
   return rv;

endmodule

module mkMemServerRW#(DmaIndication dmaIndication,
		      TagGen#(numReadClients, numReadTags) readTagGen,
		      TagGen#(numWriteClients,numWriteTags) writeTagGen,
		      Vector#(numReadClients, ObjectReadClient#(dataWidth)) readClients,
		      Vector#(numWriteClients, ObjectWriteClient#(dataWidth)) writeClients)
   (MemServer#(addrWidth, dataWidth))

   provisos (Add#(1,a__,dataWidth),
	     Add#(b__, TSub#(addrWidth, 12), 32),
	     Add#(c__, 12, addrWidth),
	     Add#(d__, addrWidth, 64),
	     Add#(e__, TSub#(addrWidth, 12), ObjectOffsetSize),
	     Add#(f__, c__, ObjectOffsetSize),
	     Add#(g__, addrWidth, 40),
	     Mul#(TDiv#(dataWidth, 8), 8, dataWidth),
	     Add#(h__, TLog#(numReadTags), 6),
	     Add#(j__, TLog#(numWriteTags), 6));

   SGListMMU#(addrWidth) sgl <- mkSGListMMU(dmaIndication);
   FIFO#(void)   addrReqFifo <- mkFIFO;

   MemReadInternal#(addrWidth,dataWidth) reader <- mkMemReadInternal(readClients, dmaIndication, sgl.addr[0], readTagGen);
   MemWriteInternal#(addrWidth,dataWidth) writer <- mkMemWriteInternal(writeClients, dmaIndication, sgl.addr[1], writeTagGen);

   rule sglistEntry;
      addrReqFifo.deq;
      let physAddr <- sgl.addr[0].response.get;
      dmaIndication.addrResponse(zeroExtend(physAddr));
   endrule

   interface DmaConfig request;
      method Action getStateDbg(ChannelType rc);
	 let rv = ?;
	 if (rc == Read)
	    rv <- reader.dbg.dbg;
	 else
	    rv <- writer.dbg.dbg;
	 dmaIndication.reportStateDbg(rv);
      endmethod
      method Action getMemoryTraffic(ChannelType rc, Bit#(32) client);
	 if (rc == Read) begin
	    let rv <- reader.dbg.getMemoryTraffic(client);
	    dmaIndication.reportMemoryTraffic(rv);
	 end
	 else begin
	    let rv <- writer.dbg.getMemoryTraffic(client);
	    dmaIndication.reportMemoryTraffic(rv);
	 end
      endmethod
      method Action sglist(Bit#(32) pref, Bit#(ObjectOffsetSize) addr, Bit#(32) len);
	 if (bad_pointer(pref))
	    dmaIndication.badPointer(pref);
`ifdef BSIM
	 let va <- pareff(pref, len);
         addr[39:32] = truncate(pref);
`endif
	 sgl.sglist(pref, addr, len);
      endmethod
      method Action region(Bit#(32) pointer, Bit#(40) barr8, Bit#(8) off8, Bit#(40) barr4, Bit#(8) off4, Bit#(40) barr0, Bit#(8) off0);
	 sgl.region(pointer,barr8,off8,barr4,off4,barr0,off0);
      endmethod
      method Action addrRequest(Bit#(32) pointer, Bit#(32) offset);
	 addrReqFifo.enq(?);
	 sgl.addr[0].request.put(tuple2(truncate(pointer), extend(offset)));
      endmethod
   endinterface

   interface MemMaster master;
      interface MemReadClient read_client = reader.read_client;
      interface MemWriteClient write_client = writer.write_client;
   endinterface
endmodule

error: pathspec 'bsv/ExperimentalMemServer.bsv' did not match any file(s) known to git


PcieTop for memwrite

PcieTop for memwrite

import Portal            :: *;
import Connectable       :: *;
import Xilinx            :: *;
import XilinxPCIE        :: *;
import Xilinx7PcieBridge :: *;
import PcieToAxiBridge   :: *;
import Top               :: *;

(* no_default_clock, no_default_reset *)
module mkPcieTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n,
                          Clock sys_clk_p,     Clock sys_clk_n,
                          Reset pci_sys_reset_n)
                         (VC707_FPGA);

   let contentId = 64'h4563686f;

   X7PcieBridgeIfc#(8) x7pcie <- mkX7PcieBridge( pci_sys_clk_p, pci_sys_clk_n, sys_clk_p, sys_clk_n, pci_sys_reset_n,
                                                 contentId );

   Reg#(Bool) interruptRequested <- mkReg(False, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);

   // instantiate user portals
   let portalTop <- mkMemwriteTop(clocked_by x7pcie.clock125, reset_by x7pcie.reset125);

   // connect them to PCIE
   mkConnection(x7pcie.portal0, portalTop.ctrl, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);

   AxiSlaveEngine#(64,8) axiSlaveEngine <- mkAxiSlaveEngine(x7pcie.pciId(), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
   mkConnection(tpl_1(x7pcie.slave), tpl_2(axiSlaveEngine.tlps), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
   mkConnection(tpl_1(axiSlaveEngine.tlps), tpl_2(x7pcie.slave), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
   mkConnection(portalTop.m_axi, axiSlaveEngine.slave3, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);

   rule requestInterrupt;
      if (portalTop.interrupt && !interruptRequested)
	 x7pcie.interrupt();
      interruptRequested <= portalTop.interrupt;
   endrule

   interface pcie = x7pcie.pcie;
   //interface ddr3 = x7pcie.ddr3;
   method leds = zeroExtend({  pack(x7pcie.isCalibrated)
			     , pack(True)
			     , pack(False)
			     , pack(x7pcie.isLinkUp)
			     });

endmodule: mkPcieTop

error: pathspec 'examples/memwrite/PcieTop.bsv' did not match any file(s) known to git


General Matrix Transpose

General Matrix Transpose

import Vector::*;
import GetPut::*;
import ConfigReg::*;

interface ITranspose#(numeric type n, type a);
   interface Put#(Vector#(n, a)) inp;
   interface Get#(Vector#(n, a)) oup;
endinterface

module mkTranspose(ITranspose#(n,a))
   provisos(
      Bits#(Vector#(n,a), __a),
      Log#(n, cntBits)
   );

   RWire#(Vector#(n, a)) rw_inp           <- mkRWire;
   Reg#(Vector#(n, a)) obuf               <- mkRegU;

   Vector#(n, Reg#(Vector#(n, a))) matrix <- replicateM(mkRegU);
   Reg#(Bit#(cntBits)) count              <- mkReg(0);
   Reg#(Bool) dir                         <- mkReg(False);
   Reg#(Bool) startOutput                 <- mkConfigReg(False);

   rule shift_input(isValid(rw_inp.wget));
      let x = fromMaybe(?, rw_inp.wget);

      if (!dir) begin
         // Row shift
         for(Integer i = 0; i < valueOf(n) - 1; i = i + 1) begin
            matrix[i] <= matrix[i + 1];
         end
         matrix[valueOf(n) - 1] <= x;

         if (startOutput) begin
            obuf <= matrix[0];
         end
      end
      else begin
         // Column shift
         for(Integer i = 0; i < valueOf(n); i = i + 1) begin
            matrix[i] <= shiftInAtN(matrix[i], x[i]);
         end

         if (startOutput) begin
            Vector#(n,a) tmp;
            for(Integer i = 0; i < valueOf(n); i = i + 1) begin
               tmp[i] = matrix[i][0];
            end
            obuf <= tmp;
         end
      end
      count <= count + 1;
   endrule

   rule do_start;
      if (count == '1)
         startOutput <= True;
   endrule

   interface Put inp = toPut(rw_inp);
   interface Get oup = interface Get;
                          method ActionValue#(Vector#(n, a)) get() if (startOutput && isValid(rw_inp.wget));
                             return obuf;
                          endmethod
                       endinterface;
endmodule

(* synthesize *)
module mkTranspose32x32(ITranspose#(32, Bit#(8)));
   (* hide *) let _x <- mkTranspose;
   return _x;
endmodule

error: pathspec 'src/mkTranspose.bsv' did not match any file(s) known to git


define a system containing the LED controller

Change-Id: I1752980698ca238360cf6b19af2c5660b0a80f61

// Copyright (c) 2014 Quanta Research Cambridge, Inc.

// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

// bsv libraries
import Vector::*;

// portz libraries
import Directory::*;
import CtrlMux::*;
import Portal::*;
import Leds::*;
import MemTypes::*;
import MemPortal::*;

// generated by tool
import LedControllerRequestWrapper::*;

// defined by user
import LedController::*;

typedef enum {LedControllerRequestPortal} IfcNames deriving (Eq,Bits);

module mkPortalTop(StdPortalTop#(addrWidth));

   // instantiate user portals
   LedController ledController <- mkLedControllerRequest();
   LedControllerRequestWrapper ledControllerRequestWrapper <- mkLedControllerRequestWrapper(LedControllerRequestPortal,ledController.request);

   Vector#(1,StdPortal) portals;
   portals[0] = ledControllerRequestWrapper.portalIfc;

   // instantiate system directory
   StdDirectory dir <- mkStdDirectory(portals);
   let ctrl_mux <- mkSlaveMux(dir,portals);

   interface interrupt = getInterruptVector(portals);
   interface slave = ctrl_mux;
   interface masters = nil;
   interface leds = ledController.leds;

endmodule : mkPortalTop

error: pathspec 'examples/leds/Top.bsv' did not match any file(s) known to git


Added BRAMTightlyCoupledMemory

Added BRAMTightlyCoupledMemory

// Copyright (c) 2016 Massachusetts Institute of Technology

// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

`include "ProcConfig.bsv"

import BRAM::*;
import ClientServer::*;
import FIFOF::*;
import FIFO::*;
import GetPut::*;
import Vector::*;

import Ehr::*;

import Abstraction::*;
import RVAmo::*;
import RVExec::*; // for scatterStore and gatherLoad
import RVTypes::*;

typedef struct {
    Bool write;
    DataByteSel addrByteSel;
    RVMemSize size;
    Bool isUnsigned;
} BramDMemPendingReq deriving (Bits, Eq, FShow);

// schedule: response.get < request.put
module mkBramDMem(Server#(RVDMemReq, RVDMemResp));
    BRAM_Configure cfg = defaultValue;
    BRAM1PortBE#(Bit#(12), Data, TDiv#(XLEN,8)) bram <- mkBRAM1ServerBE(cfg);

    Ehr#(2, Maybe#(BramDMemPendingReq)) pendingReq <- mkEhr(tagged Invalid);
    interface Put request;
        method Action put(RVDMemReq r) if (pendingReq[1] == tagged Invalid);
            Bool isLd = r.op == tagged Mem Ld;
            let {permutedDataByteEn, permutedStData} = scatterStore(truncate(r.addr), r.size, r.data);
            bram.portA.request.put( BRAMRequestBE {
                    writeen:            isLd ? 0 : permutedDataByteEn,
                    responseOnWrite:    False,
                    address:            truncate(r.addr >> valueOf(TLog#(TDiv#(XLEN,8)))), // get word address
                    datain:             permutedStData
                } );
            if (isLd) begin
                pendingReq[1] <= tagged Valid BramDMemPendingReq {
                        write: False,
                        addrByteSel: truncate(r.addr),
                        size: r.size,
                        isUnsigned: r.isUnsigned
                    };
            end
        endmethod
    endinterface
    interface Get response;
        method ActionValue#(RVDMemResp) get if (pendingReq[0] matches tagged Valid .req);
            let resp <- bram.portA.response.get;
            let data = gatherLoad(req.addrByteSel, req.size, req.isUnsigned, resp);
            pendingReq[0] <= tagged Invalid;
            return data;
        endmethod
    endinterface
endmodule

module mkBramIMem(Server#(RVIMemReq, RVIMemResp));
    BRAM_Configure cfg = defaultValue;
    BRAM1PortBE#(Bit#(12), Data, TDiv#(XLEN,8)) bram <- mkBRAM1ServerBE(cfg);

    Ehr#(2, Maybe#(BramDMemPendingReq)) pendingReq <- mkEhr(tagged Invalid);
    interface Put request;
        method Action put(RVIMemReq r) if (pendingReq[1] == tagged Invalid);
            bram.portA.request.put( BRAMRequestBE {
                    writeen:            0,
                    responseOnWrite:    False,
                    address:            truncate(r >> valueOf(TLog#(TDiv#(XLEN,8)))), // get word address
                    datain:             0
                } );
            pendingReq[1] <= tagged Valid BramDMemPendingReq {
                    write: False,
                    addrByteSel: truncate(r),
                    size: W,
                    isUnsigned: False
                };
        endmethod
    endinterface
    interface Get response;
        method ActionValue#(RVIMemResp) get if (pendingReq[0] matches tagged Valid .req);
            let resp <- bram.portA.response.get;
            Instruction inst = truncate(gatherLoad(req.addrByteSel, req.size, req.isUnsigned, resp));
            pendingReq[0] <= tagged Invalid;
            return inst;
        endmethod
    endinterface
endmodule

interface IDMem;
    interface Server#(RVIMemReq, RVIMemResp) imem;
    interface Server#(RVDMemReq, RVDMemResp) dmem;
endinterface

module mkBramIDMem(IDMem);
    BRAM_Configure cfg = defaultValue;
    BRAM2PortBE#(Bit#(12), Data, TDiv#(XLEN,8)) bram <- mkBRAM2ServerBE(cfg);

    Ehr#(2, Maybe#(BramDMemPendingReq)) pendingIReq <- mkEhr(tagged Invalid);
    Ehr#(2, Maybe#(BramDMemPendingReq)) pendingDReq <- mkEhr(tagged Invalid);

    interface Server imem;
        interface Put request;
            method Action put(RVIMemReq r) if (pendingIReq[1] == tagged Invalid);
                bram.portA.request.put( BRAMRequestBE {
                        writeen:            0,
                        responseOnWrite:    False,
                        address:            truncate(r >> valueOf(TLog#(TDiv#(XLEN,8)))), // get word address
                        datain:             0
                    } );
                pendingIReq[1] <= tagged Valid BramDMemPendingReq {
                        write: False,
                        addrByteSel: truncate(r),
                        size: W,
                        isUnsigned: False
                    };
            endmethod
        endinterface
        interface Get response;
            method ActionValue#(RVIMemResp) get if (pendingIReq[0] matches tagged Valid .req);
                let resp <- bram.portA.response.get;
                Instruction inst = truncate(gatherLoad(req.addrByteSel, req.size, req.isUnsigned, resp));
                pendingIReq[0] <= tagged Invalid;
                return inst;
            endmethod
        endinterface
    endinterface

    interface Server dmem;
        interface Put request;
            method Action put(RVDMemReq r) if (pendingDReq[1] == tagged Invalid);
                Bool isLd = r.op == tagged Mem Ld;
                let {permutedDataByteEn, permutedStData} = scatterStore(truncate(r.addr), r.size, r.data);
                bram.portA.request.put( BRAMRequestBE {
                        writeen:            isLd ? 0 : permutedDataByteEn,
                        responseOnWrite:    False,
                        address:            truncate(r.addr >> valueOf(TLog#(TDiv#(XLEN,8)))), // get word address
                        datain:             permutedStData
                    } );
                if (isLd) begin
                    pendingDReq[1] <= tagged Valid BramDMemPendingReq {
                            write: !isLd,
                            addrByteSel: truncate(r.addr),
                            size: r.size,
                            isUnsigned: r.isUnsigned
                        };
                end
            endmethod
        endinterface
        interface Get response;
            method ActionValue#(RVDMemResp) get if (pendingDReq[0] matches tagged Valid .req);
                let resp <- bram.portA.response.get;
                let data = gatherLoad(req.addrByteSel, req.size, req.isUnsigned, resp);
                pendingDReq[0] <= tagged Invalid;
                return data;
            endmethod
        endinterface
    endinterface
endmodule

interface IDMemWLoader;
    interface Server#(RVIMemReq, RVIMemResp) imem;
    interface Server#(RVDMemReq, RVDMemResp) dmem;
    interface Server#(GenericMemReq#(XLEN), GenericMemResp#(XLEN)) ext;
endinterface

typedef enum {DMem, Ext} PortBUser deriving (Bits, Eq, FShow);
module mkBramIDExtMem(IDMemWLoader);
    BRAM_Configure cfg = defaultValue;
    // BRAM2PortBE#(Bit#(12), Data, TDiv#(XLEN,8)) bram <- mkBRAM2ServerBE(cfg);
    BRAM2PortBE#(Bit#(12), Data, TDiv#(XLEN,8)) bram <- mkCustomBRAM2ServerBE(cfg);

    Ehr#(2, Maybe#(BramDMemPendingReq)) pendingIReq   <- mkEhr(tagged Invalid);
    Ehr#(2, Maybe#(BramDMemPendingReq)) pendingDReq   <- mkEhr(tagged Invalid);
    Ehr#(2, Maybe#(BramDMemPendingReq)) pendingExtReq <- mkEhr(tagged Invalid);

    // for multiplexing portB between DMem and ExtMem
    Ehr#(4, Maybe#(PortBUser)) portBReq <- mkEhr(tagged Invalid);

    rule clearDMemStResp(pendingDReq[0] matches tagged Valid .req &&& req.write &&& portBReq[0] == tagged Valid DMem);
        let ignore <- bram.portB.response.get;
        pendingDReq[0] <= tagged Invalid;
        portBReq[0] <= tagged Invalid;
    endrule

    interface Server imem;
        interface Put request;
            method Action put(RVIMemReq r) if (pendingIReq[1] == tagged Invalid);
                bram.portA.request.put( BRAMRequestBE {
                        writeen:            0,
                        responseOnWrite:    False,
                        address:            truncate(r >> valueOf(TLog#(TDiv#(XLEN,8)))), // get word address
                        datain:             0
                    } );
                pendingIReq[1] <= tagged Valid BramDMemPendingReq {
                        write: False,
                        addrByteSel: truncate(r),
                        size: W,
                        isUnsigned: False
                    };
            endmethod
        endinterface
        interface Get response;
            method ActionValue#(RVIMemResp) get if (pendingIReq[0] matches tagged Valid .req);
                let resp <- bram.portA.response.get;
                Instruction inst = truncate(gatherLoad(req.addrByteSel, req.size, req.isUnsigned, resp));
                pendingIReq[0] <= tagged Invalid;
                return inst;
            endmethod
        endinterface
    endinterface

    interface Server dmem;
        interface Put request;
            method Action put(RVDMemReq r) if (pendingDReq[1] == tagged Invalid && portBReq[2] == tagged Invalid);
                Bool isLd = r.op == tagged Mem Ld;
                let {permutedDataByteEn, permutedStData} = scatterStore(truncate(r.addr), r.size, r.data);
                bram.portB.request.put( BRAMRequestBE {
                        writeen:            isLd ? 0 : permutedDataByteEn,
                        responseOnWrite:    True,
                        address:            truncate(r.addr >> valueOf(TLog#(TDiv#(XLEN,8)))), // get word address
                        datain:             permutedStData
                    } );
                pendingDReq[1] <= tagged Valid BramDMemPendingReq {
                        write: !isLd,
                        addrByteSel: truncate(r.addr),
                        size: r.size,
                        isUnsigned: r.isUnsigned
                    };
                portBReq[2] <= tagged Valid DMem;
            endmethod
        endinterface
        interface Get response;
            method ActionValue#(RVDMemResp) get if (pendingDReq[0] matches tagged Valid .req &&& portBReq[0] == tagged Valid DMem);
                let resp <- bram.portB.response.get;
                let data = gatherLoad(req.addrByteSel, req.size, req.isUnsigned, resp);
                pendingDReq[0] <= tagged Invalid;
                portBReq[0] <= tagged Invalid;
                return data;
            endmethod
        endinterface
    endinterface

    interface Server ext;
        interface Put request;
            method Action put(GenericMemReq#(XLEN) r) if (pendingExtReq[1] == tagged Invalid && portBReq[3] == tagged Invalid);
                Bool isLd = !r.write;
                // XXX: This method assumes all accesses are word aligned
                Bit#(TLog#(TDiv#(XLEN,8))) offset = truncate(r.addr);
                if (offset != 0) begin
                    $fdisplay(stderr, "[ERROR] ExtMemReq is not word aligned");
                end

                bram.portB.request.put( BRAMRequestBE {
                        writeen:            isLd ? 0 : r.byteen,
                        responseOnWrite:    True,
                        address:            truncate(r.addr >> valueOf(TLog#(TDiv#(XLEN,8)))), // get word address
                        datain:             r.data
                    } );
                pendingExtReq[1] <= tagged Valid BramDMemPendingReq {
                        write: !isLd,
                        addrByteSel: truncate(r.addr),
`ifdef CONFIG_RV64
                        size: D,
`else
                        size: W,
`endif
                        isUnsigned: False
                    };
                portBReq[3] <= tagged Valid Ext;
            endmethod
        endinterface
        interface Get response;
            method ActionValue#(GenericMemResp#(XLEN)) get if (pendingExtReq[0] matches tagged Valid .req &&& portBReq[1] == tagged Valid Ext);
                let data <- bram.portB.response.get;
                pendingExtReq[0] <= tagged Invalid;
                portBReq[1] <= tagged Invalid;
                return GenericMemResp {
                            write: req.write,
                            data: data
                        };
            endmethod
        endinterface
    endinterface
endmodule

// My own custom implementation of BRAM2PortBE using a BRAM per byte since the
// provided implementation isn't working in Vivado at the moment.
module mkCustomBRAM2ServerBE#(BRAM_Configure cfg)(BRAM2PortBE#(addrT, dataT, numByteEnables))
        provisos (Bits#(addrT, addrSz),
                  Bits#(dataT, dataSz),
                  FShow#(addrT),
                  FShow#(dataT),
                  Mul#(byteSz, numByteEnables, dataSz),
                  Alias#(Bit#(byteSz), byteT));
    Vector#(numByteEnables, BRAM2Port#(addrT, byteT)) brams <- replicateM(mkBRAM2Server(cfg));
    interface BRAMServerBE portA;
        interface Put request;
            method Action put(BRAMRequestBE#(addrT, dataT, numByteEnables) r);
                Bool isLd = r.writeen == 0;
                Vector#(numByteEnables, byteT) data = unpack(pack(r.datain));
                Vector#(numByteEnables, Bool) write = unpack(r.writeen);
                for (Integer i = 0 ; i < valueOf(numByteEnables) ; i = i+1) begin
                    if (isLd || write[i] || r.responseOnWrite) begin
                        brams[i].portA.request.put(
                                BRAMRequest {
                                    write: write[i],
                                    responseOnWrite: r.responseOnWrite,
                                    address: r.address,
                                    datain: data[i]
                                });
                    end
                end
            endmethod
        endinterface
        interface Get response;
            method ActionValue#(dataT) get();
                Vector#(numByteEnables, byteT) data = ?;
                for (Integer i = 0 ; i < valueOf(numByteEnables) ; i = i+1) begin
                    data[i] <- brams[i].portA.response.get();
                end
                dataT result = unpack(pack(data));
                return result;
            endmethod
        endinterface
    endinterface
    interface BRAMServerBE portB;
        interface Put request;
            method Action put(BRAMRequestBE#(addrT, dataT, numByteEnables) r);
                Bool isLd = r.writeen == 0;
                Vector#(numByteEnables, byteT) data = unpack(pack(r.datain));
                Vector#(numByteEnables, Bool) write = unpack(r.writeen);
                for (Integer i = 0 ; i < valueOf(numByteEnables) ; i = i+1) begin
                    if (isLd || write[i] || r.responseOnWrite) begin
                        brams[i].portB.request.put(
                                BRAMRequest {
                                    write: write[i],
                                    responseOnWrite: r.responseOnWrite,
                                    address: r.address,
                                    datain: data[i]
                                });
                    end
                end
            endmethod
        endinterface
        interface Get response;
            method ActionValue#(dataT) get();
                Vector#(numByteEnables, byteT) data = ?;
                for (Integer i = 0 ; i < valueOf(numByteEnables) ; i = i+1) begin
                    data[i] <- brams[i].portB.response.get();
                end
                dataT result = unpack(pack(data));
                return result;
            endmethod
        endinterface
    endinterface
    method Action portAClear;
        for (Integer i = 0 ; i < valueOf(numByteEnables) ; i = i+1) begin
            brams[i].portAClear;
        end
    endmethod
    method Action portBClear;
        for (Integer i = 0 ; i < valueOf(numByteEnables) ; i = i+1) begin
            brams[i].portBClear;
        end
    endmethod
endmodule

error: pathspec 'procs/riscy-lib/BRAMTightlyCoupledMemory.bsv' did not match any file(s) known to git


TxRx module implemented with a bypassFIFOF

// Copyright (c) 2016 Cornell University

// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

import Connectable::*;
import FIFOF::*;
import SpecialFIFOs::*;
import Pipe::*;

interface TX #(type t);
   interface PipeIn#(t) u;
   interface PipeOut#(t) e;
endinterface

module mkTX (TX #(t))
   provisos (Bits#(t, tsz));
   (*hide*) FIFOF#(t) _ifc <- mkBypassFIFOF;
   interface PipeIn u = toPipeIn(_ifc);
   interface PipeOut e = toPipeOut(_ifc);
endmodule

interface RX #(type t);
   interface PipeOut#(t) u;
   interface PipeIn#(t) e;
endinterface

module mkRX (RX #(t))
   provisos (Bits#(t, tsz));
   (* hide *) FIFOF#(t) _ifc <- mkBypassFIFOF;
   interface PipeOut u = toPipeOut(_ifc);
   interface PipeIn e = toPipeIn(_ifc);
endmodule

module mkChan #(module #(FIFOF #(t)) mkFIFOF,
                PipeOut #(t) txe,
                PipeIn #(t) rxe)(Empty);
   let fifof <- mkFIFOF;
   let txe_to_fifof <- mkConnection(txe, toPipeIn(fifof));
   let fifof_to_rxe <- mkConnection(toPipeOut(fifof), rxe);
endmodule

error: pathspec 'hw/bsv/TxRx.bsv' did not match any file(s) known to git